https://bugzilla.novell.com/show_bug.cgi?id=432809
User jakub007@go2.pl added comment
https://bugzilla.novell.com/show_bug.cgi?id=432809#c10
Jakub Jozwicki changed:
What |Removed |Added
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CC| |jakub007@go2.pl
--- Comment #10 from Jakub Jozwicki 2008-10-09 13:54:27 MDT ---
I have modified arch/x86/kernel/cpu/amd_64.c:
static int __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
{
unsigned bits, ecx;
/* Multi core CPU? */
if (c->extended_cpuid_level < 0x80000008)
return 0;
#ifdef CONFIG_SMP
ecx = cpuid_ecx(0x80000008);
c->x86_max_cores = (ecx & 0xff) + 1;
/* CPU telling us the core id bits shift? */
bits = (ecx >> 12) & 0xF;
/* Otherwise recompute */
if (bits == 0) {
while ((1 << bits) < c->x86_max_cores)
bits++;
}
c->x86_coreid_bits = bits;
return 1;
#else
return 1;
#endif
}
static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
{
int mc, addr;
unsigned long value;
mc = early_init_amd_mc(c);
/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
if (c->x86_power & (1<<8))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_SYSCALL32);
#define MSR_C1E 0xc0010055
#define C1E_ON_CMP_HALT_BIT (1L << 28)
#define SMI_ON_CMP_HALT_BIT (1L << 27)
#define IO_RD (1L << 26)
#define INTR_PND_MSG_BIT (1L << 25)
#define IO_MSG_ADDR_MASK ((1L << 16)-1)
if (c->x86 == 0x11) {
rdmsrl(MSR_C1E, value);
addr = value & IO_MSG_ADDR_MASK;
if (addr==0)
addr = 0x1015; // what should be here as P_LVL3?
if (addr) {
printk(KERN_INFO "Enabling AMD C1E power management
with IO address %x\n", addr);
value &= ~INTR_PND_MSG_BIT;
value |= IO_RD;
if (mc) {
value |= C1E_ON_CMP_HALT_BIT;
value &= ~SMI_ON_CMP_HALT_BIT;
}
else {
value &= ~C1E_ON_CMP_HALT_BIT;
value |= SMI_ON_CMP_HALT_BIT;
}
wrmsrl(MSR_C1E, value);
}
else {
printk(KERN_ERR "Cannot enable AMD C1E power management
due to invalid IO address\n");
}
}
}
------------------------
Addr is 0. I have checked MSR_C1E on Windows with tool from eprotek.com and
this MSR is zero. Is there other way to enable C1E?
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