https://bugzilla.novell.com/show_bug.cgi?id=432809 Andreas Jaeger changed: What |Removed |Added ---------------------------------------------------------------------------- AssignedTo|bnc-team-screening@forge.provo.novell.com |trenn@novell.com -- Configure bugmail: https://bugzilla.novell.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.

https://bugzilla.novell.com/show_bug.cgi?id=432809 User trenn@novell.com added comment https://bugzilla.novell.com/show_bug.cgi?id=432809#c2 Thomas Renninger changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |joachim.deguara@amd.com Status|ASSIGNED |NEEDINFO Info Provider| |jakub007@go2.pl --- Comment #2 from Thomas Renninger 2008-10-08 08:14:23 MDT --- Jakub, I am very interested in this one. I always was sure C1 is entered on these (should be hlt instruction if no other C-states are found?). You may want to mail me privately, adding Joachim from AMD if you do not like to post that on lkml and linux-acpi directly. -- Configure bugmail: https://bugzilla.novell.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.

https://bugzilla.novell.com/show_bug.cgi?id=432809 User jakub007@go2.pl added comment https://bugzilla.novell.com/show_bug.cgi?id=432809#c4 --- Comment #4 from Jakub Jozwicki 2008-10-08 12:06:56 MDT --- ftp://download.intel.com/technology/IAPC/acpi/downloads/30222305.pdf Section 3.3: C1 with I/O. Maybe amdk8.sys uses C1 I/O halt with hardcoded IO Port address? -- Configure bugmail: https://bugzilla.novell.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.

https://bugzilla.novell.com/show_bug.cgi?id=432809 User jakub007@go2.pl added comment https://bugzilla.novell.com/show_bug.cgi?id=432809#c6 --- Comment #6 from Jakub Jozwicki 2008-10-08 16:24:27 MDT --- Linux enables HyperTransport Centralized Link Management Controller and then CPU cannot enter C1E and we do not see any power savings. Am I right? -- Configure bugmail: https://bugzilla.novell.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.

https://bugzilla.novell.com/show_bug.cgi?id=432809 User trenn@novell.com added comment https://bugzilla.novell.com/show_bug.cgi?id=432809#c8 --- Comment #8 from Thomas Renninger 2008-10-08 16:53:08 MDT --- AFAIK, through MSR you can only check whether C1E is supported and disable/enable it. I remember testing power consumption when C1E was disabled via MSR (as a workaround for an old kernel) and enabled. I definitely saw a power consumption change. That would mean (and it is more or less the only possibility from OS view) that C1E worked.

I've been trying to ask tech.support@amd.com for some technical help, but I was told that 'Linux is not officially supported'... Yeah, but this is practically for every Windows only supported model. I mean it's the support, they have to ask you this and then say good bye if the answer is Linux.

Joachim told me he has some news for C1E for me. He could add you into CC if you are interested. It is great to see people getting involved. -- Configure bugmail: https://bugzilla.novell.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.

https://bugzilla.novell.com/show_bug.cgi?id=432809 User jakub007@go2.pl added comment https://bugzilla.novell.com/show_bug.cgi?id=432809#c10 Jakub Jozwicki changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |jakub007@go2.pl --- Comment #10 from Jakub Jozwicki 2008-10-09 13:54:27 MDT --- I have modified arch/x86/kernel/cpu/amd_64.c: static int __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) { unsigned bits, ecx; /* Multi core CPU? */ if (c->extended_cpuid_level < 0x80000008) return 0; #ifdef CONFIG_SMP ecx = cpuid_ecx(0x80000008); c->x86_max_cores = (ecx & 0xff) + 1; /* CPU telling us the core id bits shift? */ bits = (ecx >> 12) & 0xF; /* Otherwise recompute */ if (bits == 0) { while ((1 << bits) < c->x86_max_cores) bits++; } c->x86_coreid_bits = bits; return 1; #else return 1; #endif } static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) { int mc, addr; unsigned long value; mc = early_init_amd_mc(c); /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */ if (c->x86_power & (1<<8)) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_SYSCALL32); #define MSR_C1E 0xc0010055 #define C1E_ON_CMP_HALT_BIT (1L << 28) #define SMI_ON_CMP_HALT_BIT (1L << 27) #define IO_RD (1L << 26) #define INTR_PND_MSG_BIT (1L << 25) #define IO_MSG_ADDR_MASK ((1L << 16)-1) if (c->x86 == 0x11) { rdmsrl(MSR_C1E, value); addr = value & IO_MSG_ADDR_MASK; if (addr==0) addr = 0x1015; // what should be here as P_LVL3? if (addr) { printk(KERN_INFO "Enabling AMD C1E power management with IO address %x\n", addr); value &= ~INTR_PND_MSG_BIT; value |= IO_RD; if (mc) { value |= C1E_ON_CMP_HALT_BIT; value &= ~SMI_ON_CMP_HALT_BIT; } else { value &= ~C1E_ON_CMP_HALT_BIT; value |= SMI_ON_CMP_HALT_BIT; } wrmsrl(MSR_C1E, value); } else { printk(KERN_ERR "Cannot enable AMD C1E power management due to invalid IO address\n"); } } } ------------------------ Addr is 0. I have checked MSR_C1E on Windows with tool from eprotek.com and this MSR is zero. Is there other way to enable C1E? -- Configure bugmail: https://bugzilla.novell.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.

https://bugzilla.novell.com/show_bug.cgi?id=432809 User jakub007@go2.pl added comment https://bugzilla.novell.com/show_bug.cgi?id=432809#c12 Jakub Jozwicki changed: What |Removed |Added ---------------------------------------------------------------------------- Status|NEEDINFO |ASSIGNED Info Provider|jakub007@go2.pl | --- Comment #12 from Jakub Jozwicki 2008-10-11 16:17:56 MDT --- objdump -S amdk8.sys | less /hlt: 11ab0: 8b ff mov %edi,%edi 11ab2: fb sti 11ab3: f4 hlt 11ab4: c3 ret amdk8.sys references hal.dll with WRITE_PORT_UCHAR... but we can see normal C1. Does AMD know what is inside Vista driver? -- Configure bugmail: https://bugzilla.novell.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.

https://bugzilla.novell.com/show_bug.cgi?id=432809 User trenn@novell.com added comment https://bugzilla.novell.com/show_bug.cgi?id=432809#c14 --- Comment #14 from Thomas Renninger 2009-01-30 08:28:46 MST --- BTW: C1E should get enabled via SMM BIOS code when the OS switches to ACPI mode. -- Configure bugmail: https://bugzilla.novell.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.