xf86-video-radeonhd:master: 6 commit(s)
Reporting from xf86-video-radeonhd: Radeon HD video driver
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6 commits against master at da5b9c2f...:
INSTALL | 2 -
src/rhd_driver.c | 63 +++++++++++++++++---------------------------------
src/rhd_hdmi.c | 2 -
src/rhd_mc.c | 2 -
src/rhd_regs.h | 69 +++++++++++++++++++++++++++++++++++++++----------------
5 files changed, 74 insertions(+), 64 deletions(-)
commit d0ff1c5823b3c186dd80fb65105b62bff28630e6
Author: Matthias Hopf
Hi Matthias, Matthias Hopf schrieb:
commit 2d73df84b71378bc427054397d936e66ceea6769 Author: Matthias Hopf
Date: Mon Jul 27 19:08:11 2009 +0200 Fix logic bug in sideport memory detection.
thanks - better:) A short odyssey following: Sideport memory still was not detected by the check Present = (RHDReadMC(rhdPtr, RS78_MC_MISC_UMA_CNTL) & RS78_SIDE_PORT_PRESENT_R) != 0; in line 799 of rhd_mc.c so I forced: Present = 1; there. I get a little further but then the test rhd_driver.c line 1883 bails out with "bogus" (II) RADEONHD(0): IGP sideport memory present. (WW) RADEONHD(0): IGP memory base 0xc8000000 seems to be bogus. (==) RADEONHD(0): Not Mapping IGP memory (II) RADEONHD(0): Mapped FB @ 0xd0000000 to 0x7f7a8993f000 (size 0x10000000) Not agreeing IGP memory base 0xc8000000 is bogus (it's exactly 128 MByte below 0xd0000000 so at least it's plausible to me) I removed the check at rhd_driver.c line 1883 and X started up fine, with Xorg.0.log telling: (II) RADEONHD(0): IGP sideport memory present. (**) RADEONHD(0): Mapping IGP memory @ 0xc8000000 (II) RADEONHD(0): Mapped FB @ 0xd0000000 to 0x7f24a1005000 (size 0x10000000) (The line "(**) RADEONHD(0): Mapping IGP memory @ 0xc8000000" didn't tell where IGP memory was mapped to) I noticed no change in performance though - with or without the hack video memory bandwidth is too low (horizontal tearing) for a dual monitor setup (1920x1200 and 1600x1200 both @60Hz). Greetings, Frieder -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org
On Aug 03, 09 21:34:54 +0200, Frieder Ferlemann wrote:
Fix logic bug in sideport memory detection.
thanks - better:) A short odyssey following:
Sideport memory still was not detected by the check Present = (RHDReadMC(rhdPtr, RS78_MC_MISC_UMA_CNTL) & RS78_SIDE_PORT_PRESENT_R) != 0; in line 799 of rhd_mc.c so I forced: Present = 1;
there. I get a little further but then the test rhd_driver.c line 1883 bails out with "bogus"
[...] So the issue is n-fold: 1) Why is RS78_SIDE_PORT_PRESENT_R not set (can you dump the register value in the log and see what bits are actually set?) 2) Why is is the base considered bogus? 3) Is sideport memory actually used correctly?
(II) RADEONHD(0): IGP sideport memory present. (**) RADEONHD(0): Mapping IGP memory @ 0xc8000000 (II) RADEONHD(0): Mapped FB @ 0xd0000000 to 0x7f24a1005000 (size 0x10000000)
You get a different physical (GPU) address on mapped FB than on IGP memory - which means that the mapping was unsuccessful. I don't know if this code was ever audited much - there seem to be more issues that don't work out.
(The line "(**) RADEONHD(0): Mapping IGP memory @ 0xc8000000" didn't tell where IGP memory was mapped to)
It doesn't have to. There is only one mapping, so the "Mapped FB" line will tell you, but some different area has been mapped. Yes, the log lines are... confusing.
I noticed no change in performance though - with or without the hack video memory bandwidth is too low (horizontal tearing) for a dual monitor setup (1920x1200 and 1600x1200 both @60Hz).
Yes, because you're still using the old mapping without knowing :-]
Maybe the RS78_SIDE_PORT_PRESENT_R is right and you have no sideport
memory?
Matthias
--
Matthias Hopf
On Tue, Aug 4, 2009 at 6:11 AM, Matthias Hopf
On Aug 03, 09 21:34:54 +0200, Frieder Ferlemann wrote:
Fix logic bug in sideport memory detection. thanks - better:) A short odyssey following:
Sideport memory still was not detected by the check Present = (RHDReadMC(rhdPtr, RS78_MC_MISC_UMA_CNTL) & RS78_SIDE_PORT_PRESENT_R) != 0; in line 799 of rhd_mc.c so I forced: Present = 1;
there. I get a little further but then the test rhd_driver.c line 1883 bails out with "bogus"
[...]
So the issue is n-fold:
1) Why is RS78_SIDE_PORT_PRESENT_R not set (can you dump the register value in the log and see what bits are actually set?) 2) Why is is the base considered bogus? 3) Is sideport memory actually used correctly?
(II) RADEONHD(0): IGP sideport memory present. (**) RADEONHD(0): Mapping IGP memory @ 0xc8000000 (II) RADEONHD(0): Mapped FB @ 0xd0000000 to 0x7f24a1005000 (size 0x10000000)
You get a different physical (GPU) address on mapped FB than on IGP memory - which means that the mapping was unsuccessful. I don't know if this code was ever audited much - there seem to be more issues that don't work out.
IIRC, I don't think libpciacess will let you map an arbitrary address. Alex -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org
Hi, Alex Deucher schrieb:
3) Is sideport memory actually used correctly?
(II) RADEONHD(0): IGP sideport memory present. (**) RADEONHD(0): Mapping IGP memory @ 0xc8000000 (II) RADEONHD(0): Mapped FB @ 0xd0000000 to 0x7f24a1005000 (size 0x10000000) You get a different physical (GPU) address on mapped FB than on IGP memory - which means that the mapping was unsuccessful. I don't know if this code was ever audited much - there seem to be more issues that don't work out.
IIRC, I don't think libpciacess will let you map an arbitrary address.
pci_device_map_range() returns 2 (ENOENT) near rhd_driver.c line 1898. Thanks! Frieder -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org
Hi Matthias, Matthias Hopf schrieb:
1) Why is RS78_SIDE_PORT_PRESENT_R not set (can you dump the register value in the log and see what bits are actually set?)
according to xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "RS78_MC_MISC_UMA_CNTL 0x%08x\n", RHDReadMC(rhdPtr, RS78_MC_MISC_UMA_CNTL)); it's 0x00000000 ... regardless whether the setup in BIOS is one of these: UMA UMA+Sideport <-- setting of my previous postings Sideport (I had UMA memory size set to 128kByte too)
2) Why is is the base considered bogus?
Seems the check doesn't like to map 256kByte. I changed rhd_driver.c near line 1893 - xf86DrvMsg(rhdPtr->scrnIndex, option, "Mapping IGP memory @ 0x%8.8x\n",rhdPtr->FbPhysAddress); + xf86DrvMsg(rhdPtr->scrnIndex, option, "Mapping %d kByte IGP memory @ 0x%8.8x\n", + pScrn->videoRam, rhdPtr->FbPhysAddress); so I could see the size. Probably 256kByte are 128 kByte Sideport plus 128kByte UMA.
3) Is sideport memory actually used correctly?
(II) RADEONHD(0): IGP sideport memory present. (**) RADEONHD(0): Mapping IGP memory @ 0xc8000000 (II) RADEONHD(0): Mapped FB @ 0xd0000000 to 0x7f24a1005000 (size 0x10000000)
You get a different physical (GPU) address on mapped FB than on IGP memory - which means that the mapping was unsuccessful. I don't know if this code was ever audited much - there seem to be more issues that don't work out.
(The line "(**) RADEONHD(0): Mapping IGP memory @ 0xc8000000" didn't tell where IGP memory was mapped to)
It doesn't have to. There is only one mapping, so the "Mapped FB" line will tell you, but some different area has been mapped. Yes, the log lines are... confusing.
I noticed no change in performance though - with or without the hack video memory bandwidth is too low (horizontal tearing) for a dual monitor setup (1920x1200 and 1600x1200 both @60Hz).
Yes, because you're still using the old mapping without knowing :-] Maybe the RS78_SIDE_PORT_PRESENT_R is right and you have no sideport memory?
I'm sure it's there - I looked on the package of the mainboard!! :^) And the BIOS setting of (UMA / UMA+Sideport / Sideport) makes a difference in Xorg.0.log. Appending diffs between the logs. Greetings, Frieder -----8<-----------------------------------------------
diff -u Xorg.0.log.UMA Xorg.0.log.UMA_SP
--- Xorg.0.log.UMA 2009-08-04 16:58:54.000000000 +0200 +++ Xorg.0.log.UMA_SP 2009-08-04 16:58:44.000000000 +0200 @@ -12,7 +12,7 @@ Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. -(==) Log file: "/var/log/Xorg.0.log", Time: Tue Aug 4 16:57:29 2009 +(==) Log file: "/var/log/Xorg.0.log", Time: Tue Aug 4 16:48:01 2009 (==) Using config file: "/etc/X11/xorg.conf" (==) ServerLayout "Layout[all]" (**) |-->Screen "Screen[0]" (0) @@ -97,7 +97,7 @@ (II) Loader running on linux (++) using VT number 7 -(--) PCI:*(0@1:5:0) unknown vendor (0x1002) unknown chipset (0x9610) rev 0, Mem @ 0xd8000000/134217728, 0xfdfe0000/65536, 0xfde00000/1048576, I/O @ 0x0000ee00/256 +(--) PCI:*(0@1:5:0) unknown vendor (0x1002) unknown chipset (0x9610) rev 0, Mem @ 0xd0000000/268435456, 0xfdfe0000/65536, 0xfde00000/1048576, I/O @ 0x0000ee00/256 (II) System resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] @@ -350,7 +350,7 @@ and *please* describe the problems you are seeing in your message. (--) RADEONHD(0): Detected an RS780 on an unidentified card -(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fb1799b5000 (size 0x00010000) +(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fa788e61000 (size 0x00010000) (II) RADEONHD(0): Getting BIOS copy from legacy VBIOS location (II) RADEONHD(0): ATOM BIOS Rom: SubsystemVendorID: 0x1002 SubsystemID: 0x1002 @@ -361,11 +361,11 @@ (II) RADEONHD(0): Analog TV Default Mode: 1 (II) RADEONHD(0): Found default TV Mode NTSC -(--) RADEONHD(0): VideoRAM: 131072 kByte +(--) RADEONHD(0): VideoRAM: 262144 kByte (II) RADEONHD(0): Framebuffer space used by Firmware (kb): 16 -(II) RADEONHD(0): Start of VRAM area used by Firmware: 0x7ffc000 +(II) RADEONHD(0): Start of VRAM area used by Firmware: 0xfffc000 (II) RADEONHD(0): AtomBIOS requests 16kB of VRAM scratch space -(II) RADEONHD(0): AtomBIOS VRAM scratch base: 0x7ffc000 +(II) RADEONHD(0): AtomBIOS VRAM scratch base: 0xfffc000 (II) RADEONHD(0): Default Engine Clock: 600000 (II) RADEONHD(0): Default Memory Clock: 400000 (II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Output: 1200000 @@ -568,13 +568,13 @@ [32] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [33] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [34] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] -(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fb1799b5000 (size 0x00010000) +(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fa788e61000 (size 0x00010000) (II) RADEONHD(0): RS78_MC_MISC_UMA_CNTL 0x00000000 (II) RADEONHD(0): IGP sideport memory RS780 forcing Present. (II) RADEONHD(0): IGP sideport memory present. -(**) RADEONHD(0): Mapping 131072 kByte IGP memory @ 0xd0000000 +(**) RADEONHD(0): Mapping 262144 kByte IGP memory @ 0xc8000000 (**) RADEONHD(0): pci_device_map_range() failed 2. -(II) RADEONHD(0): Mapped FB @ 0xd8000000 to 0x7fb16d531000 (size 0x08000000) +(II) RADEONHD(0): Mapped FB @ 0xd0000000 to 0x7fa775214000 (size 0x10000000) (II) RADEONHD(0): Attempting to enable power management (II) RADEONHD(0): Current Engine Clock: 594280 -----8<----------------------------------------------- and now the diff between UMA+Sideport and Sideport only which nicely shows that higher clock is used:
diff -u Xorg.0.log.UMA_SP Xorg.0.log.SP --- Xorg.0.log.UMA_SP 2009-08-04 16:58:44.000000000 +0200 +++ Xorg.0.log.SP 2009-08-04 17:04:27.000000000 +0200 @@ -12,7 +12,7 @@ Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. -(==) Log file: "/var/log/Xorg.0.log", Time: Tue Aug 4 16:48:01 2009 +(==) Log file: "/var/log/Xorg.0.log", Time: Tue Aug 4 17:03:32 2009 (==) Using config file: "/etc/X11/xorg.conf" (==) ServerLayout "Layout[all]" (**) |-->Screen "Screen[0]" (0) @@ -97,7 +97,7 @@ (II) Loader running on linux (++) using VT number 7
-(--) PCI:*(0@1:5:0) unknown vendor (0x1002) unknown chipset (0x9610) rev 0, Mem @ 0xd0000000/268435456, 0xfdfe0000/65536, 0xfde00000/1048576, I/O @ 0x0000ee00/256 +(--) PCI:*(0@1:5:0) unknown vendor (0x1002) unknown chipset (0x9610) rev 0, Mem @ 0xd8000000/134217728, 0xfdfe0000/65536, 0xfde00000/1048576, I/O @ 0x0000ee00/256 (II) System resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] @@ -350,7 +350,7 @@ and *please* describe the problems you are seeing in your message. (--) RADEONHD(0): Detected an RS780 on an unidentified card -(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fa788e61000 (size 0x00010000) +(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fd6151da000 (size 0x00010000) (II) RADEONHD(0): Getting BIOS copy from legacy VBIOS location (II) RADEONHD(0): ATOM BIOS Rom: SubsystemVendorID: 0x1002 SubsystemID: 0x1002 @@ -361,13 +361,13 @@ (II) RADEONHD(0): Analog TV Default Mode: 1 (II) RADEONHD(0): Found default TV Mode NTSC -(--) RADEONHD(0): VideoRAM: 262144 kByte +(--) RADEONHD(0): VideoRAM: 131072 kByte (II) RADEONHD(0): Framebuffer space used by Firmware (kb): 16 -(II) RADEONHD(0): Start of VRAM area used by Firmware: 0xfffc000 +(II) RADEONHD(0): Start of VRAM area used by Firmware: 0x7ffc000 (II) RADEONHD(0): AtomBIOS requests 16kB of VRAM scratch space -(II) RADEONHD(0): AtomBIOS VRAM scratch base: 0xfffc000 +(II) RADEONHD(0): AtomBIOS VRAM scratch base: 0x7ffc000 (II) RADEONHD(0): Default Engine Clock: 600000 -(II) RADEONHD(0): Default Memory Clock: 400000 +(II) RADEONHD(0): Default Memory Clock: 533000 (II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Output: 1200000 (II) RADEONHD(0): Minimum Pixel ClockPLL Frequency Output: 0 (II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Input: 13500 @@ -417,7 +417,7 @@ (II) RADEONHD(0): Scary bits: Estimated MinEngineClock 250000 kHz (II) RADEONHD(0): Scary bits: Estimated MinMemoryClock 250000 kHz (II) RADEONHD(0): Default Engine Clock: 600000 -(II) RADEONHD(0): Default Memory Clock: 400000 +(II) RADEONHD(0): Default Memory Clock: 533000 (II) RADEONHD(0): Current Engine Clock: 594280 (EE) RADEONHD(0): AtomBIOS command table 47 does not exist (II) RADEONHD(0): Query for AtomBIOS Exec: not implemented @@ -426,23 +426,23 @@ (II) RADEONHD(0): Power Management: Raw Ranges (II) RADEONHD(0): Minimum 250000 kHz / 250000 kHz / 0.000 V (II) RADEONHD(0): Maximum 0 kHz / 0 kHz / 0.000 V -(II) RADEONHD(0): Default 600000 kHz / 400000 kHz / 0.000 V +(II) RADEONHD(0): Default 600000 kHz / 533000 kHz / 0.000 V (II) RADEONHD(0): PowerPlayInfo Revision 0401 (II) RADEONHD(0): Power Management: Validated Ranges (II) RADEONHD(0): Minimum 250000 kHz / 250000 kHz / 0.000 V -(II) RADEONHD(0): Maximum 600000 kHz / 500000 kHz / 0.000 V -(II) RADEONHD(0): Default 600000 kHz / 400000 kHz / 0.000 V +(II) RADEONHD(0): Maximum 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Default 600000 kHz / 533000 kHz / 0.000 V (II) RADEONHD(0): Power Management: Known Good Configurations (II) RADEONHD(0): 1 500000 kHz / 500000 kHz / 0.000 V (II) RADEONHD(0): Power Management: Final Levels (II) RADEONHD(0): Off 250000 kHz / 250000 kHz / 0.000 V -(II) RADEONHD(0): Idle 300000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Slow2D 600000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Fast2D 600000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Slow3D 600000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Fast3D 600000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Max3D 600000 kHz / 500000 kHz / 0.000 V -(II) RADEONHD(0): User 600000 kHz / 400000 kHz / 0.000 V +(II) RADEONHD(0): Idle 300000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Slow2D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Fast2D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Slow3D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Fast3D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Max3D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): User 600000 kHz / 533000 kHz / 0.000 V (II) RADEONHD(0): Connector[0] {RHD_CONNECTOR_VGA, "VGA CRT1", RHD_DDC_0, RHD_HPD_NONE, { RHD_OUTPUT_DACA, RHD_OUTPUT_NONE } } (II) RADEONHD(0): Connector[1] {RHD_CONNECTOR_DVI, "DUAL_LINK_DVI_D DFP1", RHD_DDC_1, RHD_HPD_0, { RHD_OUTPUT_KLDSKP_LVTMA, RHD_OUTPUT_NONE } } (--) RADEONHD(0): Attaching Output DAC A to Connector VGA 1 @@ -568,13 +568,12 @@ [32] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [33] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [34] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] -(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fa788e61000 (size 0x00010000) +(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fd6151da000 (size 0x00010000) (II) RADEONHD(0): RS78_MC_MISC_UMA_CNTL 0x00000000 (II) RADEONHD(0): IGP sideport memory RS780 forcing Present. (II) RADEONHD(0): IGP sideport memory present. -(**) RADEONHD(0): Mapping 262144 kByte IGP memory @ 0xc8000000 -(**) RADEONHD(0): pci_device_map_range() failed 2. -(II) RADEONHD(0): Mapped FB @ 0xd0000000 to 0x7fa775214000 (size 0x10000000) +(**) RADEONHD(0): Mapping 131072 kByte IGP memory @ 0xd8000000 +(II) RADEONHD(0): Mapped FB @ 0xd8000000 to 0x7fd608d56000 (size 0x08000000) (II) RADEONHD(0): Attempting to enable power management (II) RADEONHD(0): Current Engine Clock: 594280 -----8<----------------------------------------------- and now for the UMA only versus Sideport only setting:
diff -u Xorg.0.log.UMA Xorg.0.log.SP --- Xorg.0.log.UMA 2009-08-04 16:58:54.000000000 +0200 +++ Xorg.0.log.SP 2009-08-04 17:04:27.000000000 +0200 @@ -12,7 +12,7 @@ Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. -(==) Log file: "/var/log/Xorg.0.log", Time: Tue Aug 4 16:57:29 2009 +(==) Log file: "/var/log/Xorg.0.log", Time: Tue Aug 4 17:03:32 2009 (==) Using config file: "/etc/X11/xorg.conf" (==) ServerLayout "Layout[all]" (**) |-->Screen "Screen[0]" (0) @@ -350,7 +350,7 @@ and *please* describe the problems you are seeing in your message. (--) RADEONHD(0): Detected an RS780 on an unidentified card -(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fb1799b5000 (size 0x00010000) +(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fd6151da000 (size 0x00010000) (II) RADEONHD(0): Getting BIOS copy from legacy VBIOS location (II) RADEONHD(0): ATOM BIOS Rom: SubsystemVendorID: 0x1002 SubsystemID: 0x1002 @@ -367,7 +367,7 @@ (II) RADEONHD(0): AtomBIOS requests 16kB of VRAM scratch space (II) RADEONHD(0): AtomBIOS VRAM scratch base: 0x7ffc000 (II) RADEONHD(0): Default Engine Clock: 600000 -(II) RADEONHD(0): Default Memory Clock: 400000 +(II) RADEONHD(0): Default Memory Clock: 533000 (II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Output: 1200000 (II) RADEONHD(0): Minimum Pixel ClockPLL Frequency Output: 0 (II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Input: 13500 @@ -417,7 +417,7 @@ (II) RADEONHD(0): Scary bits: Estimated MinEngineClock 250000 kHz (II) RADEONHD(0): Scary bits: Estimated MinMemoryClock 250000 kHz (II) RADEONHD(0): Default Engine Clock: 600000 -(II) RADEONHD(0): Default Memory Clock: 400000 +(II) RADEONHD(0): Default Memory Clock: 533000 (II) RADEONHD(0): Current Engine Clock: 594280 (EE) RADEONHD(0): AtomBIOS command table 47 does not exist (II) RADEONHD(0): Query for AtomBIOS Exec: not implemented @@ -426,23 +426,23 @@ (II) RADEONHD(0): Power Management: Raw Ranges (II) RADEONHD(0): Minimum 250000 kHz / 250000 kHz / 0.000 V (II) RADEONHD(0): Maximum 0 kHz / 0 kHz / 0.000 V -(II) RADEONHD(0): Default 600000 kHz / 400000 kHz / 0.000 V +(II) RADEONHD(0): Default 600000 kHz / 533000 kHz / 0.000 V (II) RADEONHD(0): PowerPlayInfo Revision 0401 (II) RADEONHD(0): Power Management: Validated Ranges (II) RADEONHD(0): Minimum 250000 kHz / 250000 kHz / 0.000 V -(II) RADEONHD(0): Maximum 600000 kHz / 500000 kHz / 0.000 V -(II) RADEONHD(0): Default 600000 kHz / 400000 kHz / 0.000 V +(II) RADEONHD(0): Maximum 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Default 600000 kHz / 533000 kHz / 0.000 V (II) RADEONHD(0): Power Management: Known Good Configurations (II) RADEONHD(0): 1 500000 kHz / 500000 kHz / 0.000 V (II) RADEONHD(0): Power Management: Final Levels (II) RADEONHD(0): Off 250000 kHz / 250000 kHz / 0.000 V -(II) RADEONHD(0): Idle 300000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Slow2D 600000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Fast2D 600000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Slow3D 600000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Fast3D 600000 kHz / 400000 kHz / 0.000 V -(II) RADEONHD(0): Max3D 600000 kHz / 500000 kHz / 0.000 V -(II) RADEONHD(0): User 600000 kHz / 400000 kHz / 0.000 V +(II) RADEONHD(0): Idle 300000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Slow2D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Fast2D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Slow3D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Fast3D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): Max3D 600000 kHz / 533000 kHz / 0.000 V +(II) RADEONHD(0): User 600000 kHz / 533000 kHz / 0.000 V (II) RADEONHD(0): Connector[0] {RHD_CONNECTOR_VGA, "VGA CRT1", RHD_DDC_0, RHD_HPD_NONE, { RHD_OUTPUT_DACA, RHD_OUTPUT_NONE } } (II) RADEONHD(0): Connector[1] {RHD_CONNECTOR_DVI, "DUAL_LINK_DVI_D DFP1", RHD_DDC_1, RHD_HPD_0, { RHD_OUTPUT_KLDSKP_LVTMA, RHD_OUTPUT_NONE } } (--) RADEONHD(0): Attaching Output DAC A to Connector VGA 1 @@ -568,13 +568,12 @@ [32] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [33] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [34] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] -(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fb1799b5000 (size 0x00010000) +(II) RADEONHD(0): Mapped IO @ 0xfdfe0000 to 0x7fd6151da000 (size 0x00010000) (II) RADEONHD(0): RS78_MC_MISC_UMA_CNTL 0x00000000 (II) RADEONHD(0): IGP sideport memory RS780 forcing Present. (II) RADEONHD(0): IGP sideport memory present. -(**) RADEONHD(0): Mapping 131072 kByte IGP memory @ 0xd0000000 -(**) RADEONHD(0): pci_device_map_range() failed 2. -(II) RADEONHD(0): Mapped FB @ 0xd8000000 to 0x7fb16d531000 (size 0x08000000) +(**) RADEONHD(0): Mapping 131072 kByte IGP memory @ 0xd8000000 +(II) RADEONHD(0): Mapped FB @ 0xd8000000 to 0x7fd608d56000 (size 0x08000000) (II) RADEONHD(0): Attempting to enable power management (II) RADEONHD(0): Current Engine Clock: 594280
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On Aug 04, 09 18:01:42 +0200, Frieder Ferlemann wrote:
Maybe the RS78_SIDE_PORT_PRESENT_R is right and you have no sideport memory?
I'm sure it's there - I looked on the package of the mainboard!! :^)
:-P Don't you dare to come with facts.
-(--) PCI:*(0@1:5:0) unknown vendor (0x1002) unknown chipset (0x9610) rev 0, Mem @ 0xd8000000/134217728, 0xfdfe0000/65536, 0xfde00000/1048576, I/O @ 0x0000ee00/256 +(--) PCI:*(0@1:5:0) unknown vendor (0x1002) unknown chipset (0x9610) rev 0, Mem @ 0xd0000000/268435456, 0xfdfe0000/65536, 0xfde00000/1048576, I/O @ 0x0000ee00/256 -(--) RADEONHD(0): VideoRAM: 131072 kByte +(--) RADEONHD(0): VideoRAM: 262144 kByte
Hm. Fascinating. In the end it actually works... though as far as I read the code this is not true...
and now the diff between UMA+Sideport and Sideport only which nicely shows that higher clock is used:
Fascinating :-)
Sorry, no experience on my side here, and we don't have any sideport
enabled hardware here AFAIK.
Matthias
--
Matthias Hopf
participants (4)
-
Alex Deucher
-
Frieder Ferlemann
-
Matthias Hopf
-
mhopf@kemper.freedesktop.org