GNU 'make' uses implicit variables to perform some tasks. For example CC to define the compiler, and RM to remove a file: http://www.gnu.org/s/hello/manual/make/Implicit-Variables.html On openSUSE 11.2, I can redefine CC as expected. Whatever I define there gets used to do the compile. If I am compiling a binary from multiple sources, my CC gets used for each object file: myBinary: a.o b.o c.o myBinary is correctly created. Since the make rule led to making the three object files, it will also automatically delete them when done. Which it does. But it will not use the RM variable to do this. It seems to use some other definition. At least if I redefine RM (in the same place I defined CC), my definition is never used. All I am really trying to accomplish is to not have the make process echo the rm command when it removes objects it make to satisfy some rule. So, I want to define it as: RM = @rm -f I guess the built-in rule uses 'rm' instead of $(RM). At least it is acting that way. Another odd thing is that the Gnu docs say the default RM command is 'rm -f'. But I see 'rm' being used. Am I looking in the wrong place to redefine RM? Yours sincerely, Roger Oberholtzer OPQ Systems / Ramböll RST Office: Int +46 10-615 60 20 Mobile: Int +46 70-815 1696 roger.oberholtzer@ramboll.se ________________________________________ Ramböll Sverige AB Krukmakargatan 21 P.O. Box 17009 SE-104 62 Stockholm, Sweden www.rambollrst.se -- To unsubscribe, e-mail: opensuse-programming+unsubscribe@opensuse.org For additional commands, e-mail: opensuse-programming+help@opensuse.org