On Fri, Sep 18, 2009 at 3:35 AM, Ales Fiala
Folks,
What is the meaning of the RV515_MC_STATUS:MC_IDLE bit?
The RV515/516 spec says it "Indicates that there are no pending or in-process requests in the MC."
There is code in RHDMCSetup() and RHDRestoreMC() that does the following: ASSERT((RHDRegRead(rhdPtr, D1VGA_CONTROL) & D1VGA_MODE_ENABLE) != D1VGA_MODE_ENABLE); ASSERT((RHDRegRead(rhdPtr, D2VGA_CONTROL) & D2VGA_MODE_ENABLE) != D2VGA_MODE_ENABLE); ASSERT((RHDRegRead(rhdPtr, D1CRTC_CONTROL) & 0x1) != 0x1); ASSERT((RHDRegRead(rhdPtr, D2CRTC_CONTROL) & 0x1) != 0x1); ASSERT(RHDMCIdle(rhdPtr, 1));
I am getting infrequent failures in the last assertion, indicating that the MC is not idle. I verified that both the VGA anc CRTC controllers are indeed disabled, Yet the MC_IDLE bit is still wiggling. I wrote a little piece of code that reads it in a tight loop and indeed it comes on every 10-20 reads and then immediately goes off.
So if the CRTC and VGA controllers are not reading the memory, why is the MC not idle?
Could it be that even if the screen is not being refreshed, the dynamic RAM still needs to be refreshed to keep it from losing its contents?
If this is the case, I think that this code is flawed. It shouldn't assume that the MC is idle when the CRTC and VGA controllers are disabled.
Thanks for any insight into this.
I've just been issues with something in a similiar area, have a look at VGA_RENDER_CONTROL 0x300 register, make sure bits 16,17 are cleared also, as the vga rendered may be accessing memory. Dave. -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org