Hello community,
here is the log from the commit of package gcc43
checked in at Fri Aug 8 17:28:21 CEST 2008.
--------
--- gcc43/cross-avr-gcc43.changes 2008-07-17 17:47:38.000000000 +0200
+++ /mounts/work_src_done/STABLE/gcc43/cross-avr-gcc43.changes 2008-08-06 23:05:03.000000000 +0200
@@ -1,0 +2,19 @@
+Tue Aug 5 14:13:09 CEST 2008 - rguenther@suse.de
+
+- Update to gcc-4_3-branch head (r138797).
+- Add patches for context sensitive vector keyword support (IBM).
+- Add patch for PR36613.
+
+-------------------------------------------------------------------
+Fri Jul 25 18:05:49 CEST 2008 - rguenther@suse.de
+
+- Update to gcc-4_3-branch head (r138144).
+- Add patches for early complete loop unrolling.
+
+-------------------------------------------------------------------
+Mon Jul 21 16:00:22 CEST 2008 - rguenther@suse.de
+
+- Add patches to support SSE5 vectorized shift instructions.
+- Add patch for PR36765.
+
+-------------------------------------------------------------------
cross-hppa-gcc-icecream-backend.changes: same change
cross-i386-gcc-icecream-backend.changes: same change
cross-ia64-gcc-icecream-backend.changes: same change
cross-ppc64-gcc-icecream-backend.changes: same change
cross-ppc-gcc-icecream-backend.changes: same change
cross-s390-gcc-icecream-backend.changes: same change
cross-s390x-gcc-icecream-backend.changes: same change
cross-spu-gcc.changes: same change
cross-spu-gcc-static.changes: same change
cross-x86_64-gcc-icecream-backend.changes: same change
gcc43.changes: same change
libgcj43.changes: same change
Old:
----
gcc-4.3.2-20080715.tar.bz2
New:
----
amd-cunroll-1.diff
amd-cunroll-2.diff
amd-SSE5-shift-ppc-1.diff
amd-SSE5-shift-ppc-2.diff
gcc-4.3.2-20080806.tar.bz2
ibm-vector-keyword-1
ibm-vector-keyword-2
ibm-vector-keyword-3
pr36613.diff
pr36765.diff
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ cross-avr-gcc43.spec ++++++
--- /var/tmp/diff_new_pack.xT1721/_old 2008-08-08 17:26:45.000000000 +0200
+++ /var/tmp/diff_new_pack.xT1721/_new 2008-08-08 17:26:45.000000000 +0200
@@ -1,10 +1,17 @@
#
-# spec file for package cross-avr-gcc43 (Version 4.3.2_20080715)
+# spec file for package cross-avr-gcc43 (Version 4.3.2_20080806)
#
# Copyright (c) 2008 SUSE LINUX Products GmbH, Nuernberg, Germany.
-# This file and all modifications and additions to the pristine
-# package are under the same license as the package itself.
#
+# All modifications and additions to the file contributed by third parties
+# remain the property of their copyright owners, unless otherwise agreed
+# upon. The license for this file, and modifications and additions to the
+# file, is the same license as for the pristine package itself (unless the
+# license for the pristine package is not an Open Source License, in which
+# case the license is the MIT License). An "Open Source License" is a
+# license that conforms to the Open Source Definition (Version 1.9)
+# published by the Open Source Initiative.
+
# Please submit bugfixes or comments via http://bugs.opensuse.org/
#
@@ -14,7 +21,6 @@
#
# spec file for package gcc (Version 4.0.1)
#
-# Copyright (c) 2005 SUSE Linux AG, Nuernberg, Germany.
# This file and all modifications and additions to the pristine
# package are under the same license as the package itself.
#
@@ -55,7 +61,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc
Url: http://gcc.gnu.org/
License: BSD 3-Clause; GPL v2 or later; LGPL v2.1 or later; X11/MIT
-Version: 4.3.2_20080715
+Version: 4.3.2_20080806
Release: 1
%define gcc_version %(echo %version | sed 's/_.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -87,6 +93,8 @@
Patch30: Wunprototyped-calls.diff
Patch31: pr27799.diff
Patch39: pr36343.diff
+Patch40: pr36765.diff
+Patch41: pr36613.diff
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -100,6 +108,11 @@
Patch72: pr34043-3.diff
Patch73: pr34043-4.diff
Patch74: pr34043-5.diff
+Patch75: amd-SSE5-shift-ppc-1.diff
+Patch76: amd-SSE5-shift-ppc-2.diff
+Patch77: amd-SSE5-shift.diff
+Patch78: amd-cunroll-1.diff
+Patch79: amd-cunroll-2.diff
# Patches for Intel features
Patch80: intel303993-aes.diff
# Patches for IBM features
@@ -112,6 +125,9 @@
Patch96: pr36745.diff
Patch97: pr36822.diff
Patch98: ibm-mpower4.diff
+Patch99: ibm-vector-keyword-1
+Patch100: ibm-vector-keyword-2
+Patch101: ibm-vector-keyword-3
# LIBJAVA-DELETE-BEGIN
%description
@@ -169,6 +185,8 @@
%patch30
%patch31
%patch39
+%patch40
+%patch41
%patch51
%patch55
%patch57
@@ -179,6 +197,11 @@
%patch72
%patch73
%patch74 -p1
+%patch75
+%patch76
+%patch77
+%patch78
+%patch79
%patch80
%patch90
%patch91
@@ -189,6 +212,9 @@
%patch96
%patch97
#%patch98
+%patch99
+%patch100
+%patch101
%build
# Avoid rebuilding of generated files
@@ -355,7 +381,6 @@
--with-long-double-128 \
%endif
%if "%{TARGET_ARCH}" == "powerpc64"
- --with-cpu=default64 \
--enable-secureplt \
--with-long-double-128 \
%endif
@@ -390,6 +415,16 @@
%defattr(-,root,root)
%{_prefix}
%changelog
+* Tue Aug 05 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138797).
+- Add patches for context sensitive vector keyword support (IBM).
+- Add patch for PR36613.
+* Fri Jul 25 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138144).
+- Add patches for early complete loop unrolling.
+* Mon Jul 21 2008 rguenther@suse.de
+- Add patches to support SSE5 vectorized shift instructions.
+- Add patch for PR36765.
* Tue Jul 15 2008 rguenther@suse.de
- Update to gcc-4_3-branch head (r137837).
- Make it build on SLES9.
++++++ cross-hppa-gcc-icecream-backend.spec ++++++
--- /var/tmp/diff_new_pack.xT1721/_old 2008-08-08 17:26:45.000000000 +0200
+++ /var/tmp/diff_new_pack.xT1721/_new 2008-08-08 17:26:45.000000000 +0200
@@ -1,10 +1,17 @@
#
-# spec file for package cross-hppa-gcc-icecream-backend (Version 4.3.2_20080715)
+# spec file for package cross-hppa-gcc-icecream-backend (Version 4.3.2_20080806)
#
# Copyright (c) 2008 SUSE LINUX Products GmbH, Nuernberg, Germany.
-# This file and all modifications and additions to the pristine
-# package are under the same license as the package itself.
#
+# All modifications and additions to the file contributed by third parties
+# remain the property of their copyright owners, unless otherwise agreed
+# upon. The license for this file, and modifications and additions to the
+# file, is the same license as for the pristine package itself (unless the
+# license for the pristine package is not an Open Source License, in which
+# case the license is the MIT License). An "Open Source License" is a
+# license that conforms to the Open Source Definition (Version 1.9)
+# published by the Open Source Initiative.
+
# Please submit bugfixes or comments via http://bugs.opensuse.org/
#
@@ -34,7 +41,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc
Url: http://gcc.gnu.org/
License: BSD 3-Clause; GPL v2 or later; LGPL v2.1 or later; X11/MIT
-Version: 4.3.2_20080715
+Version: 4.3.2_20080806
Release: 1
%define gcc_version %(echo %version | sed 's/_.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -66,6 +73,8 @@
Patch30: Wunprototyped-calls.diff
Patch31: pr27799.diff
Patch39: pr36343.diff
+Patch40: pr36765.diff
+Patch41: pr36613.diff
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -79,6 +88,11 @@
Patch72: pr34043-3.diff
Patch73: pr34043-4.diff
Patch74: pr34043-5.diff
+Patch75: amd-SSE5-shift-ppc-1.diff
+Patch76: amd-SSE5-shift-ppc-2.diff
+Patch77: amd-SSE5-shift.diff
+Patch78: amd-cunroll-1.diff
+Patch79: amd-cunroll-2.diff
# Patches for Intel features
Patch80: intel303993-aes.diff
# Patches for IBM features
@@ -91,6 +105,9 @@
Patch96: pr36745.diff
Patch97: pr36822.diff
Patch98: ibm-mpower4.diff
+Patch99: ibm-vector-keyword-1
+Patch100: ibm-vector-keyword-2
+Patch101: ibm-vector-keyword-3
# LIBJAVA-DELETE-BEGIN
%description
@@ -151,6 +168,8 @@
%patch30
%patch31
%patch39
+%patch40
+%patch41
%patch51
%patch55
%patch57
@@ -161,6 +180,11 @@
%patch72
%patch73
%patch74 -p1
+%patch75
+%patch76
+%patch77
+%patch78
+%patch79
%patch80
%patch90
%patch91
@@ -171,6 +195,9 @@
%patch96
%patch97
#%patch98
+%patch99
+%patch100
+%patch101
%build
# Avoid rebuilding of generated files
@@ -337,7 +364,6 @@
--with-long-double-128 \
%endif
%if "%{TARGET_ARCH}" == "powerpc64"
- --with-cpu=default64 \
--enable-secureplt \
--with-long-double-128 \
%endif
@@ -410,6 +436,16 @@
/usr/share/icecream-envs
%changelog
+* Tue Aug 05 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138797).
+- Add patches for context sensitive vector keyword support (IBM).
+- Add patch for PR36613.
+* Fri Jul 25 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138144).
+- Add patches for early complete loop unrolling.
+* Mon Jul 21 2008 rguenther@suse.de
+- Add patches to support SSE5 vectorized shift instructions.
+- Add patch for PR36765.
* Tue Jul 15 2008 rguenther@suse.de
- Update to gcc-4_3-branch head (r137837).
- Make it build on SLES9.
cross-i386-gcc-icecream-backend.spec: same change
cross-ia64-gcc-icecream-backend.spec: same change
cross-ppc64-gcc-icecream-backend.spec: same change
cross-ppc-gcc-icecream-backend.spec: same change
cross-s390-gcc-icecream-backend.spec: same change
cross-s390x-gcc-icecream-backend.spec: same change
++++++ cross-spu-gcc.spec ++++++
--- /var/tmp/diff_new_pack.xT1721/_old 2008-08-08 17:26:46.000000000 +0200
+++ /var/tmp/diff_new_pack.xT1721/_new 2008-08-08 17:26:46.000000000 +0200
@@ -1,10 +1,17 @@
#
-# spec file for package cross-spu-gcc (Version 4.3.2_20080715)
+# spec file for package cross-spu-gcc (Version 4.3.2_20080806)
#
# Copyright (c) 2008 SUSE LINUX Products GmbH, Nuernberg, Germany.
-# This file and all modifications and additions to the pristine
-# package are under the same license as the package itself.
#
+# All modifications and additions to the file contributed by third parties
+# remain the property of their copyright owners, unless otherwise agreed
+# upon. The license for this file, and modifications and additions to the
+# file, is the same license as for the pristine package itself (unless the
+# license for the pristine package is not an Open Source License, in which
+# case the license is the MIT License). An "Open Source License" is a
+# license that conforms to the Open Source Definition (Version 1.9)
+# published by the Open Source Initiative.
+
# Please submit bugfixes or comments via http://bugs.opensuse.org/
#
@@ -45,7 +52,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc
Url: http://gcc.gnu.org/
License: GPL v2 or later
-Version: 4.3.2_20080715
+Version: 4.3.2_20080806
Release: 1
%define gcc_version %(echo %version | sed 's/_.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -77,6 +84,8 @@
Patch30: Wunprototyped-calls.diff
Patch31: pr27799.diff
Patch39: pr36343.diff
+Patch40: pr36765.diff
+Patch41: pr36613.diff
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -90,6 +99,11 @@
Patch72: pr34043-3.diff
Patch73: pr34043-4.diff
Patch74: pr34043-5.diff
+Patch75: amd-SSE5-shift-ppc-1.diff
+Patch76: amd-SSE5-shift-ppc-2.diff
+Patch77: amd-SSE5-shift.diff
+Patch78: amd-cunroll-1.diff
+Patch79: amd-cunroll-2.diff
# Patches for Intel features
Patch80: intel303993-aes.diff
# Patches for IBM features
@@ -102,6 +116,9 @@
Patch96: pr36745.diff
Patch97: pr36822.diff
Patch98: ibm-mpower4.diff
+Patch99: ibm-vector-keyword-1
+Patch100: ibm-vector-keyword-2
+Patch101: ibm-vector-keyword-3
# LIBJAVA-DELETE-BEGIN
%description
@@ -154,6 +171,8 @@
%patch30
%patch31
%patch39
+%patch40
+%patch41
%patch51
%patch55
%patch57
@@ -164,6 +183,11 @@
%patch72
%patch73
%patch74 -p1
+%patch75
+%patch76
+%patch77
+%patch78
+%patch79
%patch80
%patch90
%patch91
@@ -174,6 +198,9 @@
%patch96
%patch97
#%patch98
+%patch99
+%patch100
+%patch101
%build
# Avoid rebuilding of generated files
@@ -340,7 +367,6 @@
--with-long-double-128 \
%endif
%if "%{TARGET_ARCH}" == "powerpc64"
- --with-cpu=default64 \
--enable-secureplt \
--with-long-double-128 \
%endif
@@ -375,6 +401,16 @@
%defattr(-,root,root)
%{_prefix}
%changelog
+* Tue Aug 05 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138797).
+- Add patches for context sensitive vector keyword support (IBM).
+- Add patch for PR36613.
+* Fri Jul 25 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138144).
+- Add patches for early complete loop unrolling.
+* Mon Jul 21 2008 rguenther@suse.de
+- Add patches to support SSE5 vectorized shift instructions.
+- Add patch for PR36765.
* Tue Jul 15 2008 rguenther@suse.de
- Update to gcc-4_3-branch head (r137837).
- Make it build on SLES9.
++++++ cross-spu-gcc-static.spec ++++++
--- /var/tmp/diff_new_pack.xT1721/_old 2008-08-08 17:26:46.000000000 +0200
+++ /var/tmp/diff_new_pack.xT1721/_new 2008-08-08 17:26:46.000000000 +0200
@@ -1,10 +1,17 @@
#
-# spec file for package cross-spu-gcc-static (Version 4.3.2_20080715)
+# spec file for package cross-spu-gcc-static (Version 4.3.2_20080806)
#
# Copyright (c) 2008 SUSE LINUX Products GmbH, Nuernberg, Germany.
-# This file and all modifications and additions to the pristine
-# package are under the same license as the package itself.
#
+# All modifications and additions to the file contributed by third parties
+# remain the property of their copyright owners, unless otherwise agreed
+# upon. The license for this file, and modifications and additions to the
+# file, is the same license as for the pristine package itself (unless the
+# license for the pristine package is not an Open Source License, in which
+# case the license is the MIT License). An "Open Source License" is a
+# license that conforms to the Open Source Definition (Version 1.9)
+# published by the Open Source Initiative.
+
# Please submit bugfixes or comments via http://bugs.opensuse.org/
#
@@ -14,7 +21,6 @@
#
# spec file for package gcc (Version 4.0.1)
#
-# Copyright (c) 2005 SUSE Linux AG, Nuernberg, Germany.
# This file and all modifications and additions to the pristine
# package are under the same license as the package itself.
#
@@ -55,7 +61,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc
Url: http://gcc.gnu.org/
License: GPL v2 or later
-Version: 4.3.2_20080715
+Version: 4.3.2_20080806
Release: 1
%define gcc_version %(echo %version | sed 's/_.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -87,6 +93,8 @@
Patch30: Wunprototyped-calls.diff
Patch31: pr27799.diff
Patch39: pr36343.diff
+Patch40: pr36765.diff
+Patch41: pr36613.diff
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -100,6 +108,11 @@
Patch72: pr34043-3.diff
Patch73: pr34043-4.diff
Patch74: pr34043-5.diff
+Patch75: amd-SSE5-shift-ppc-1.diff
+Patch76: amd-SSE5-shift-ppc-2.diff
+Patch77: amd-SSE5-shift.diff
+Patch78: amd-cunroll-1.diff
+Patch79: amd-cunroll-2.diff
# Patches for Intel features
Patch80: intel303993-aes.diff
# Patches for IBM features
@@ -112,6 +125,9 @@
Patch96: pr36745.diff
Patch97: pr36822.diff
Patch98: ibm-mpower4.diff
+Patch99: ibm-vector-keyword-1
+Patch100: ibm-vector-keyword-2
+Patch101: ibm-vector-keyword-3
# LIBJAVA-DELETE-BEGIN
%description
@@ -164,6 +180,8 @@
%patch30
%patch31
%patch39
+%patch40
+%patch41
%patch51
%patch55
%patch57
@@ -174,6 +192,11 @@
%patch72
%patch73
%patch74 -p1
+%patch75
+%patch76
+%patch77
+%patch78
+%patch79
%patch80
%patch90
%patch91
@@ -184,6 +207,9 @@
%patch96
%patch97
#%patch98
+%patch99
+%patch100
+%patch101
%build
# Avoid rebuilding of generated files
@@ -350,7 +376,6 @@
--with-long-double-128 \
%endif
%if "%{TARGET_ARCH}" == "powerpc64"
- --with-cpu=default64 \
--enable-secureplt \
--with-long-double-128 \
%endif
@@ -385,6 +410,16 @@
%defattr(-,root,root)
%{_prefix}
%changelog
+* Tue Aug 05 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138797).
+- Add patches for context sensitive vector keyword support (IBM).
+- Add patch for PR36613.
+* Fri Jul 25 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138144).
+- Add patches for early complete loop unrolling.
+* Mon Jul 21 2008 rguenther@suse.de
+- Add patches to support SSE5 vectorized shift instructions.
+- Add patch for PR36765.
* Tue Jul 15 2008 rguenther@suse.de
- Update to gcc-4_3-branch head (r137837).
- Make it build on SLES9.
++++++ cross-x86_64-gcc-icecream-backend.spec ++++++
--- /var/tmp/diff_new_pack.xT1721/_old 2008-08-08 17:26:46.000000000 +0200
+++ /var/tmp/diff_new_pack.xT1721/_new 2008-08-08 17:26:46.000000000 +0200
@@ -1,10 +1,17 @@
#
-# spec file for package cross-x86_64-gcc-icecream-backend (Version 4.3.2_20080715)
+# spec file for package cross-x86_64-gcc-icecream-backend (Version 4.3.2_20080806)
#
# Copyright (c) 2008 SUSE LINUX Products GmbH, Nuernberg, Germany.
-# This file and all modifications and additions to the pristine
-# package are under the same license as the package itself.
#
+# All modifications and additions to the file contributed by third parties
+# remain the property of their copyright owners, unless otherwise agreed
+# upon. The license for this file, and modifications and additions to the
+# file, is the same license as for the pristine package itself (unless the
+# license for the pristine package is not an Open Source License, in which
+# case the license is the MIT License). An "Open Source License" is a
+# license that conforms to the Open Source Definition (Version 1.9)
+# published by the Open Source Initiative.
+
# Please submit bugfixes or comments via http://bugs.opensuse.org/
#
@@ -34,7 +41,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc
Url: http://gcc.gnu.org/
License: BSD 3-Clause; GPL v2 or later; LGPL v2.1 or later; X11/MIT
-Version: 4.3.2_20080715
+Version: 4.3.2_20080806
Release: 1
%define gcc_version %(echo %version | sed 's/_.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -66,6 +73,8 @@
Patch30: Wunprototyped-calls.diff
Patch31: pr27799.diff
Patch39: pr36343.diff
+Patch40: pr36765.diff
+Patch41: pr36613.diff
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -79,6 +88,11 @@
Patch72: pr34043-3.diff
Patch73: pr34043-4.diff
Patch74: pr34043-5.diff
+Patch75: amd-SSE5-shift-ppc-1.diff
+Patch76: amd-SSE5-shift-ppc-2.diff
+Patch77: amd-SSE5-shift.diff
+Patch78: amd-cunroll-1.diff
+Patch79: amd-cunroll-2.diff
# Patches for Intel features
Patch80: intel303993-aes.diff
# Patches for IBM features
@@ -91,6 +105,9 @@
Patch96: pr36745.diff
Patch97: pr36822.diff
Patch98: ibm-mpower4.diff
+Patch99: ibm-vector-keyword-1
+Patch100: ibm-vector-keyword-2
+Patch101: ibm-vector-keyword-3
# LIBJAVA-DELETE-BEGIN
%description
@@ -151,6 +168,8 @@
%patch30
%patch31
%patch39
+%patch40
+%patch41
%patch51
%patch55
%patch57
@@ -161,6 +180,11 @@
%patch72
%patch73
%patch74 -p1
+%patch75
+%patch76
+%patch77
+%patch78
+%patch79
%patch80
%patch90
%patch91
@@ -171,6 +195,9 @@
%patch96
%patch97
#%patch98
+%patch99
+%patch100
+%patch101
%build
# Avoid rebuilding of generated files
@@ -337,7 +364,6 @@
--with-long-double-128 \
%endif
%if "%{TARGET_ARCH}" == "powerpc64"
- --with-cpu=default64 \
--enable-secureplt \
--with-long-double-128 \
%endif
@@ -410,6 +436,16 @@
/usr/share/icecream-envs
%changelog
+* Tue Aug 05 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138797).
+- Add patches for context sensitive vector keyword support (IBM).
+- Add patch for PR36613.
+* Fri Jul 25 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138144).
+- Add patches for early complete loop unrolling.
+* Mon Jul 21 2008 rguenther@suse.de
+- Add patches to support SSE5 vectorized shift instructions.
+- Add patch for PR36765.
* Tue Jul 15 2008 rguenther@suse.de
- Update to gcc-4_3-branch head (r137837).
- Make it build on SLES9.
++++++ gcc43.spec ++++++
--- /var/tmp/diff_new_pack.xT1721/_old 2008-08-08 17:26:46.000000000 +0200
+++ /var/tmp/diff_new_pack.xT1721/_new 2008-08-08 17:26:46.000000000 +0200
@@ -1,10 +1,17 @@
#
-# spec file for package gcc43 (Version 4.3.2_20080715)
+# spec file for package gcc43 (Version 4.3.2_20080806)
#
# Copyright (c) 2008 SUSE LINUX Products GmbH, Nuernberg, Germany.
-# This file and all modifications and additions to the pristine
-# package are under the same license as the package itself.
#
+# All modifications and additions to the file contributed by third parties
+# remain the property of their copyright owners, unless otherwise agreed
+# upon. The license for this file, and modifications and additions to the
+# file, is the same license as for the pristine package itself (unless the
+# license for the pristine package is not an Open Source License, in which
+# case the license is the MIT License). An "Open Source License" is a
+# license that conforms to the Open Source Definition (Version 1.9)
+# published by the Open Source Initiative.
+
# Please submit bugfixes or comments via http://bugs.opensuse.org/
#
@@ -107,7 +114,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc
Url: http://gcc.gnu.org/
License: GPL v3 or later
-Version: 4.3.2_20080715
+Version: 4.3.2_20080806
Release: 1
%define gcc_version %(echo %version | sed 's/_.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -150,6 +157,8 @@
Patch30: Wunprototyped-calls.diff
Patch31: pr27799.diff
Patch39: pr36343.diff
+Patch40: pr36765.diff
+Patch41: pr36613.diff
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -163,6 +172,11 @@
Patch72: pr34043-3.diff
Patch73: pr34043-4.diff
Patch74: pr34043-5.diff
+Patch75: amd-SSE5-shift-ppc-1.diff
+Patch76: amd-SSE5-shift-ppc-2.diff
+Patch77: amd-SSE5-shift.diff
+Patch78: amd-cunroll-1.diff
+Patch79: amd-cunroll-2.diff
# Patches for Intel features
Patch80: intel303993-aes.diff
# Patches for IBM features
@@ -175,6 +189,9 @@
Patch96: pr36745.diff
Patch97: pr36822.diff
Patch98: ibm-mpower4.diff
+Patch99: ibm-vector-keyword-1
+Patch100: ibm-vector-keyword-2
+Patch101: ibm-vector-keyword-3
# LIBJAVA-DELETE-BEGIN
%description
@@ -1328,6 +1345,8 @@
%patch30
%patch31
%patch39
+%patch40
+%patch41
%patch51
%patch55
%patch57
@@ -1338,6 +1357,11 @@
%patch72
%patch73
%patch74 -p1
+%patch75
+%patch76
+%patch77
+%patch78
+%patch79
%patch80
%patch90
%patch91
@@ -1348,6 +1372,9 @@
%patch96
%patch97
#%patch98
+%patch99
+%patch100
+%patch101
%build
# Avoid rebuilding of generated files
@@ -1514,7 +1541,6 @@
--with-long-double-128 \
%endif
%if "%{TARGET_ARCH}" == "powerpc64"
- --with-cpu=default64 \
--enable-secureplt \
--with-long-double-128 \
%endif
@@ -1548,6 +1574,8 @@
mv %{GCCDIST}/libstdc++-v3/testsuite/libstdc++.log %{GCCDIST}/libstdc++-v3/testsuite/libstdc++-abi.log
mv %{GCCDIST}/libstdc++-v3/testsuite/libstdc++.sum %{GCCDIST}/libstdc++-v3/testsuite/libstdc++-abi.sum
make -k check $PARALLEL || true
+mkdir ../testresults
+../contrib/test_summary > ../testresults/test_summary.txt
%endif
%install
@@ -1738,7 +1766,6 @@
mv $l.new $l
done
%if %{run_tests}
-mkdir ../testresults
cp `find . -name "*.sum"` ../testresults/
cp `find . -name "*.log" \! -name "config.log" |grep -v 'acats/tests' ` ../testresults/
chmod 644 ../testresults/*
@@ -2355,11 +2382,22 @@
%files -n gcc43-testresults
%defattr(-,root,root)
+%doc testresults/test_summary.txt
%doc testresults/*.sum
%doc testresults/*.log
%endif
%changelog
+* Tue Aug 05 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138797).
+- Add patches for context sensitive vector keyword support (IBM).
+- Add patch for PR36613.
+* Fri Jul 25 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138144).
+- Add patches for early complete loop unrolling.
+* Mon Jul 21 2008 rguenther@suse.de
+- Add patches to support SSE5 vectorized shift instructions.
+- Add patch for PR36765.
* Tue Jul 15 2008 rguenther@suse.de
- Update to gcc-4_3-branch head (r137837).
- Make it build on SLES9.
++++++ libgcj43.spec ++++++
--- /var/tmp/diff_new_pack.xT1721/_old 2008-08-08 17:26:46.000000000 +0200
+++ /var/tmp/diff_new_pack.xT1721/_new 2008-08-08 17:26:46.000000000 +0200
@@ -1,10 +1,17 @@
#
-# spec file for package libgcj43 (Version 4.3.2_20080715)
+# spec file for package libgcj43 (Version 4.3.2_20080806)
#
# Copyright (c) 2008 SUSE LINUX Products GmbH, Nuernberg, Germany.
-# This file and all modifications and additions to the pristine
-# package are under the same license as the package itself.
#
+# All modifications and additions to the file contributed by third parties
+# remain the property of their copyright owners, unless otherwise agreed
+# upon. The license for this file, and modifications and additions to the
+# file, is the same license as for the pristine package itself (unless the
+# license for the pristine package is not an Open Source License, in which
+# case the license is the MIT License). An "Open Source License" is a
+# license that conforms to the Open Source Definition (Version 1.9)
+# published by the Open Source Initiative.
+
# Please submit bugfixes or comments via http://bugs.opensuse.org/
#
@@ -16,7 +23,6 @@
#
# spec file for package gcc (Version 4.3.x)
#
-# Copyright (c) 2005 SUSE LINUX Products GmbH, Nuernberg, Germany.
# This file and all modifications and additions to the pristine
# package are under the same license as the package itself.
#
@@ -119,7 +125,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc
Url: http://gcc.gnu.org/
License: GPL v2 or later; LGPL v2.1 or later
-Version: 4.3.2_20080715
+Version: 4.3.2_20080806
Release: 1
%define gcc_version %(echo %version | sed 's/_.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -162,6 +168,8 @@
Patch30: Wunprototyped-calls.diff
Patch31: pr27799.diff
Patch39: pr36343.diff
+Patch40: pr36765.diff
+Patch41: pr36613.diff
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -175,6 +183,11 @@
Patch72: pr34043-3.diff
Patch73: pr34043-4.diff
Patch74: pr34043-5.diff
+Patch75: amd-SSE5-shift-ppc-1.diff
+Patch76: amd-SSE5-shift-ppc-2.diff
+Patch77: amd-SSE5-shift.diff
+Patch78: amd-cunroll-1.diff
+Patch79: amd-cunroll-2.diff
# Patches for Intel features
Patch80: intel303993-aes.diff
# Patches for IBM features
@@ -187,6 +200,9 @@
Patch96: pr36745.diff
Patch97: pr36822.diff
Patch98: ibm-mpower4.diff
+Patch99: ibm-vector-keyword-1
+Patch100: ibm-vector-keyword-2
+Patch101: ibm-vector-keyword-3
Summary: Java Runtime Library for gcc
Group: System/Libraries
%define gcj_sover 9
@@ -567,6 +583,8 @@
%patch30
%patch31
%patch39
+%patch40
+%patch41
%patch51
%patch55
%patch57
@@ -577,6 +595,11 @@
%patch72
%patch73
%patch74 -p1
+%patch75
+%patch76
+%patch77
+%patch78
+%patch79
%patch80
%patch90
%patch91
@@ -587,6 +610,9 @@
%patch96
%patch97
#%patch98
+%patch99
+%patch100
+%patch101
%build
# Avoid rebuilding of generated files
@@ -753,7 +779,6 @@
--with-long-double-128 \
%endif
%if "%{TARGET_ARCH}" == "powerpc64"
- --with-cpu=default64 \
--enable-secureplt \
--with-long-double-128 \
%endif
@@ -787,6 +812,8 @@
mv %{GCCDIST}/libstdc++-v3/testsuite/libstdc++.log %{GCCDIST}/libstdc++-v3/testsuite/libstdc++-abi.log
mv %{GCCDIST}/libstdc++-v3/testsuite/libstdc++.sum %{GCCDIST}/libstdc++-v3/testsuite/libstdc++-abi.sum
make -k check $PARALLEL || true
+mkdir ../testresults
+../contrib/test_summary > ../testresults/test_summary.txt
%endif
%install
@@ -911,7 +938,6 @@
mv $l.new $l
done
%if %{run_tests}
-mkdir ../testresults
cp `find . -name "*.sum"` ../testresults/
cp `find . -name "*.log" \! -name "config.log" |grep -v 'acats/tests' ` ../testresults/
chmod 644 ../testresults/*
@@ -1168,11 +1194,22 @@
%files -n gcc43-testresults
%defattr(-,root,root)
+%doc testresults/test_summary.txt
%doc testresults/*.sum
%doc testresults/*.log
%endif
%changelog
+* Tue Aug 05 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138797).
+- Add patches for context sensitive vector keyword support (IBM).
+- Add patch for PR36613.
+* Fri Jul 25 2008 rguenther@suse.de
+- Update to gcc-4_3-branch head (r138144).
+- Add patches for early complete loop unrolling.
+* Mon Jul 21 2008 rguenther@suse.de
+- Add patches to support SSE5 vectorized shift instructions.
+- Add patch for PR36765.
* Tue Jul 15 2008 rguenther@suse.de
- Update to gcc-4_3-branch head (r137837).
- Make it build on SLES9.
++++++ amd-cunroll-1.diff ++++++
++++ 766 lines (skipped)
++++++ amd-cunroll-2.diff ++++++
2008-04-29 Richard Guenther
PR tree-optimization/36078
* tree-ssa-loop-ivcanon.c (tree_unroll_loops_completely):
Update virtual SSA form after cleaning up the CFG.
* gfortran.fortran-torture/compile/pr36078.f90: New testcase.
Index: gcc/testsuite/gfortran.fortran-torture/compile/pr36078.f90
===================================================================
*** gcc/testsuite/gfortran.fortran-torture/compile/pr36078.f90 (revision 0)
--- gcc/testsuite/gfortran.fortran-torture/compile/pr36078.f90 (revision 0)
***************
*** 0 ****
--- 1,22 ----
+ subroutine foo(func,p,eval)
+ real(kind=kind(1.0d0)), dimension(3,0:4,0:4,0:4) :: p
+ logical(kind=kind(.true.)), dimension(5,5,5) :: eval
+ interface
+ subroutine func(values,pt)
+ real(kind=kind(1.0d0)), dimension(:), intent(out) :: values
+ real(kind=kind(1.0d0)), dimension(:,:), intent(in) :: pt
+ end subroutine
+ end interface
+ real(kind=kind(1.0d0)), dimension(125,3) :: pt
+ integer(kind=kind(1)) :: n_pt
+
+ n_pt = 1
+ pt(1:n_pt,:) = &
+ reshape( &
+ pack( &
+ transpose(reshape(p,(/3,125/))), &
+ spread(reshape(eval,(/125/)),dim=2,ncopies=3)), &
+ (/n_pt,3/))
+
+ end subroutine
+ end
Index: gcc/tree-ssa-loop-ivcanon.c
===================================================================
*** gcc/tree-ssa-loop-ivcanon.c (revision 134791)
--- gcc/tree-ssa-loop-ivcanon.c (working copy)
*************** tree_unroll_loops_completely (bool may_i
*** 366,372 ****
/* This will take care of removing completely unrolled loops
from the loop structures so we can continue unrolling now
innermost loops. */
! cleanup_tree_cfg ();
/* Clean up the information about numbers of iterations, since
complete unrolling might have invalidated it. */
--- 366,373 ----
/* This will take care of removing completely unrolled loops
from the loop structures so we can continue unrolling now
innermost loops. */
! if (cleanup_tree_cfg ())
! update_ssa (TODO_update_ssa_only_virtuals);
/* Clean up the information about numbers of iterations, since
complete unrolling might have invalidated it. */
++++++ amd-SSE5-shift.diff ++++++
++++ 1351 lines (skipped)
++++ between gcc43/amd-SSE5-shift.diff
++++ and /mounts/work_src_done/STABLE/gcc43/amd-SSE5-shift.diff
++++++ amd-SSE5-shift-ppc-1.diff ++++++
2008-03-09 Ira Rosen
* config/rs6000/rs6000.c (builtin_description): Rename vector
left shift operations.
* config/rs6000/altivec.md (UNSPEC_VSL): Remove.
(altivec_vsl): Rename to ...
(ashl<mode>3): ... new name.
(mulv4sf3, mulv4si3, negv4sf2): Replace gen_altivec_vslw with
gen_ashlv4si3.
(absv4sf2): Convert to use ashift:V4SI instead of UNSPEC_VSL.
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 133050)
+++ gcc/config/rs6000/rs6000.c (revision 133051)
@@ -7090,9 +7090,9 @@ static struct builtin_description bdesc_
{ MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
- { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
- { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
- { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
+ { MASK_ALTIVEC, CODE_FOR_ashlv16qi3, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
+ { MASK_ALTIVEC, CODE_FOR_ashlv8hi3, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
+ { MASK_ALTIVEC, CODE_FOR_ashlv4si3, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
{ MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
Index: gcc/config/rs6000/altivec.md
===================================================================
--- gcc/config/rs6000/altivec.md (revision 133050)
+++ gcc/config/rs6000/altivec.md (revision 133051)
@@ -64,7 +64,6 @@ (define_constants
(UNSPEC_VPKUWUS 102)
(UNSPEC_VPKSWUS 103)
(UNSPEC_VRL 104)
- (UNSPEC_VSL 107)
(UNSPEC_VSLV4SI 110)
(UNSPEC_VSLO 111)
(UNSPEC_VSR 118)
@@ -576,7 +575,7 @@ (define_expand "mulv4sf3"
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
neg0 = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
- emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
+ emit_insn (gen_ashlv4si3 (neg0, neg0, neg0));
/* Use the multiply-add. */
emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
@@ -635,7 +634,7 @@ (define_expand "mulv4si3"
high_product = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
- emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
+ emit_insn (gen_ashlv4si3 (high_product, high_product, sixteen));
emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
@@ -1221,15 +1220,6 @@ (define_insn "altivec_vrl"
"vrl %0,%1,%2"
[(set_attr "type" "vecsimple")])
-(define_insn "altivec_vsl"
- [(set (match_operand:VI 0 "register_operand" "=v")
- (unspec:VI [(match_operand:VI 1 "register_operand" "v")
- (match_operand:VI 2 "register_operand" "v")]
- UNSPEC_VSL))]
- "TARGET_ALTIVEC"
- "vsl %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
(define_insn "altivec_vsl"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
@@ -1248,6 +1238,14 @@ (define_insn "altivec_vslo"
"vslo %0,%1,%2"
[(set_attr "type" "vecperm")])
+(define_insn "ashl<mode>3"
+ [(set (match_operand:VI 0 "register_operand" "=v")
+ (ashift:VI (match_operand:VI 1 "register_operand" "v")
+ (match_operand:VI 2 "register_operand" "v") ))]
+ "TARGET_ALTIVEC"
+ "vsl %0,%1,%2"
+ [(set_attr "type" "vecsimple")])
+
(define_insn "lshr<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
(lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
@@ -2039,7 +2037,7 @@ (define_expand "absv4sf2"
[(set (match_dup 2)
(vec_duplicate:V4SI (const_int -1)))
(set (match_dup 3)
- (unspec:V4SI [(match_dup 2) (match_dup 2)] UNSPEC_VSL))
+ (ashift:V4SI (match_dup 2) (match_dup 2)))
(set (match_operand:V4SF 0 "register_operand" "=v")
(and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
(match_operand:V4SF 1 "register_operand" "v")))]
@@ -2642,7 +2640,7 @@ (define_expand "negv4sf2"
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
neg0 = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
- emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
+ emit_insn (gen_ashlv4si3 (neg0, neg0, neg0));
/* XOR */
emit_insn (gen_xorv4sf3 (operands[0],
++++++ amd-SSE5-shift-ppc-2.diff ++++++
2008-05-14 Michael Meissner
Paolo Bonzini <bonzini at gnu dot org>
* config/rs6000/rs6000.c (bdesc_2arg): Change the names of vector
shift patterns.
* config/rs6000/altivec.md (vashl<mode>3): Rename from
ashl<mode>3.
(vlshr<mode>3): Rename from vlshr<mode>3.
(vashr<mode>3): Rename from vashr<mode>3.
(mulv4sf3): Change the names of vector shift patterns.
(mulv4si3): Ditto.
(negv4sf2): Ditt.
* config/spu/spu.c (spu_initialize_trampoline): Rename vector
shift insns.
* config/spu/spu-builtins.def (SI_SHLH): Rename vector shift
insns.
(SI_SHLHI): Ditto.
(SI_SHL): Ditto.
(SI_SHLI): Ditto.
(SI_ROTH): Ditto.
(SI_ROTHI): Ditto.
(SI_ROT): Ditto.
(SI_ROTI): Ditto.
(SPU_RL_0): Ditto.
(SPU_RL_1): Ditto.
(SPU_RL_2): Ditto.
(SPU_RL_3): Ditto.
(SPU_RL_4): Ditto.
(SPU_RL_5): Ditto.
(SPU_RL_6): Ditto.
(SPU_RL_7): Ditto.
(SPU_SL_0): Ditto.
(SPU_SL_1): Ditto.
(SPU_SL_2): Ditto.
(SPU_SL_3): Ditto.
(SPU_SL_4): Ditto.
(SPU_SL_5): Ditto.
(SPU_SL_6): Ditto.
(SPU_SL_7): Ditto.
* config/spu/spu.md (v): New iterator macro to add v for vector types.
(floatunssidf2_internal): Change vector/vector shift names.
(floatunsdidf2_internal): Ditto.
(mulv8hi3): Ditto.
(ashrdi3): Ditto.
(ashrti3): Ditto.
(cgt_df): Ditto.
(cgt_v2df): Ditto.
(dftsv): Ditto.
(vashl<mode>3): Rename from ashl<mode>3.
(vashr<mode>3): Rename from ashr<mode>3.
(vlshr<mode>3): Rename from lshr<mode>3.
(vrotl<mode>3): Rename from rotl<mode>3.
Index: gcc/config/spu/spu.c
===================================================================
--- gcc/config/spu/spu.c (revision 135303)
+++ gcc/config/spu/spu.c (revision 135304)
@@ -4799,7 +4799,7 @@ spu_initialize_trampoline (rtx tramp, rt
insnc = force_reg (V4SImode, array_to_constant (V4SImode, insna));
emit_insn (gen_shufb (shuf, fnaddr, cxt, shufc));
- emit_insn (gen_rotlv4si3 (rotl, shuf, spu_const (V4SImode, 7)));
+ emit_insn (gen_vrotlv4si3 (rotl, shuf, spu_const (V4SImode, 7)));
emit_insn (gen_movv4si (mask, spu_const (V4SImode, 0xffff << 7)));
emit_insn (gen_selb (insn, insnc, rotl, mask));
Index: gcc/config/spu/spu-builtins.def
===================================================================
--- gcc/config/spu/spu-builtins.def (revision 135303)
+++ gcc/config/spu/spu-builtins.def (revision 135304)
@@ -107,19 +107,19 @@ DEF_BUILTIN (SI_NOR, CODE_FOR_no
DEF_BUILTIN (SI_EQV, CODE_FOR_eqv_v16qi, "si_eqv", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SELB, CODE_FOR_selb, "si_selb", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHUFB, CODE_FOR_shufb, "si_shufb", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
-DEF_BUILTIN (SI_SHLH, CODE_FOR_ashlv8hi3, "si_shlh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
-DEF_BUILTIN (SI_SHLHI, CODE_FOR_ashlv8hi3, "si_shlhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
-DEF_BUILTIN (SI_SHL, CODE_FOR_ashlv4si3, "si_shl", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
-DEF_BUILTIN (SI_SHLI, CODE_FOR_ashlv4si3, "si_shli", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
+DEF_BUILTIN (SI_SHLH, CODE_FOR_vashlv8hi3, "si_shlh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_SHLHI, CODE_FOR_vashlv8hi3, "si_shlhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
+DEF_BUILTIN (SI_SHL, CODE_FOR_vashlv4si3, "si_shl", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_SHLI, CODE_FOR_vashlv4si3, "si_shli", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_SHLQBI, CODE_FOR_shlqbi_ti, "si_shlqbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHLQBII, CODE_FOR_shlqbi_ti, "si_shlqbii", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_SHLQBY, CODE_FOR_shlqby_ti, "si_shlqby", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHLQBYI, CODE_FOR_shlqby_ti, "si_shlqbyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_SHLQBYBI, CODE_FOR_shlqbybi_ti, "si_shlqbybi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
-DEF_BUILTIN (SI_ROTH, CODE_FOR_rotlv8hi3, "si_roth", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
-DEF_BUILTIN (SI_ROTHI, CODE_FOR_rotlv8hi3, "si_rothi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
-DEF_BUILTIN (SI_ROT, CODE_FOR_rotlv4si3, "si_rot", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
-DEF_BUILTIN (SI_ROTI, CODE_FOR_rotlv4si3, "si_roti", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
+DEF_BUILTIN (SI_ROTH, CODE_FOR_vrotlv8hi3, "si_roth", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_ROTHI, CODE_FOR_vrotlv8hi3, "si_rothi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
+DEF_BUILTIN (SI_ROT, CODE_FOR_vrotlv4si3, "si_rot", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
+DEF_BUILTIN (SI_ROTI, CODE_FOR_vrotlv4si3, "si_roti", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTQBY, CODE_FOR_rotqby_ti, "si_rotqby", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTQBYI, CODE_FOR_rotqby_ti, "si_rotqbyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTQBYBI, CODE_FOR_rotqbybi_ti, "si_rotqbybi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
@@ -536,14 +536,14 @@ DEF_BUILTIN (SPU_XOR_13, CODE_
DEF_BUILTIN (SPU_XOR_14, CODE_FOR_xorv4si3, "spu_xor_14", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_XOR_15, CODE_FOR_xorv4si3, "spu_xor_15", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RL, CODE_FOR_nothing, "spu_rl", B_OVERLOAD, _A1(SPU_BTI_VOID))
-DEF_BUILTIN (SPU_RL_0, CODE_FOR_rotlv8hi3, "spu_rl_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_V8HI))
-DEF_BUILTIN (SPU_RL_1, CODE_FOR_rotlv8hi3, "spu_rl_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
-DEF_BUILTIN (SPU_RL_2, CODE_FOR_rotlv4si3, "spu_rl_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_V4SI))
-DEF_BUILTIN (SPU_RL_3, CODE_FOR_rotlv4si3, "spu_rl_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
-DEF_BUILTIN (SPU_RL_4, CODE_FOR_rotlv8hi3, "spu_rl_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTHI))
-DEF_BUILTIN (SPU_RL_5, CODE_FOR_rotlv8hi3, "spu_rl_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
-DEF_BUILTIN (SPU_RL_6, CODE_FOR_rotlv4si3, "spu_rl_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
-DEF_BUILTIN (SPU_RL_7, CODE_FOR_rotlv4si3, "spu_rl_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
+DEF_BUILTIN (SPU_RL_0, CODE_FOR_vrotlv8hi3, "spu_rl_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_V8HI))
+DEF_BUILTIN (SPU_RL_1, CODE_FOR_vrotlv8hi3, "spu_rl_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
+DEF_BUILTIN (SPU_RL_2, CODE_FOR_vrotlv4si3, "spu_rl_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_V4SI))
+DEF_BUILTIN (SPU_RL_3, CODE_FOR_vrotlv4si3, "spu_rl_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
+DEF_BUILTIN (SPU_RL_4, CODE_FOR_vrotlv8hi3, "spu_rl_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTHI))
+DEF_BUILTIN (SPU_RL_5, CODE_FOR_vrotlv8hi3, "spu_rl_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
+DEF_BUILTIN (SPU_RL_6, CODE_FOR_vrotlv4si3, "spu_rl_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
+DEF_BUILTIN (SPU_RL_7, CODE_FOR_vrotlv4si3, "spu_rl_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW, CODE_FOR_nothing, "spu_rlqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLQW_0, CODE_FOR_rotqbi_ti, "spu_rlqw_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_1, CODE_FOR_rotqbi_ti, "spu_rlqw_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
@@ -629,14 +629,14 @@ DEF_BUILTIN (SPU_RLMASKQWBYTEBC_7, CODE_
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_8, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_9, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_SL, CODE_FOR_nothing, "spu_sl", B_OVERLOAD, _A1(SPU_BTI_VOID))
-DEF_BUILTIN (SPU_SL_0, CODE_FOR_ashlv8hi3, "spu_sl_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
-DEF_BUILTIN (SPU_SL_1, CODE_FOR_ashlv8hi3, "spu_sl_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
-DEF_BUILTIN (SPU_SL_2, CODE_FOR_ashlv4si3, "spu_sl_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
-DEF_BUILTIN (SPU_SL_3, CODE_FOR_ashlv4si3, "spu_sl_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
-DEF_BUILTIN (SPU_SL_4, CODE_FOR_ashlv8hi3, "spu_sl_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
-DEF_BUILTIN (SPU_SL_5, CODE_FOR_ashlv8hi3, "spu_sl_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
-DEF_BUILTIN (SPU_SL_6, CODE_FOR_ashlv4si3, "spu_sl_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
-DEF_BUILTIN (SPU_SL_7, CODE_FOR_ashlv4si3, "spu_sl_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
+DEF_BUILTIN (SPU_SL_0, CODE_FOR_vashlv8hi3, "spu_sl_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
+DEF_BUILTIN (SPU_SL_1, CODE_FOR_vashlv8hi3, "spu_sl_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
+DEF_BUILTIN (SPU_SL_2, CODE_FOR_vashlv4si3, "spu_sl_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
+DEF_BUILTIN (SPU_SL_3, CODE_FOR_vashlv4si3, "spu_sl_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
+DEF_BUILTIN (SPU_SL_4, CODE_FOR_vashlv8hi3, "spu_sl_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
+DEF_BUILTIN (SPU_SL_5, CODE_FOR_vashlv8hi3, "spu_sl_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
+DEF_BUILTIN (SPU_SL_6, CODE_FOR_vashlv4si3, "spu_sl_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
+DEF_BUILTIN (SPU_SL_7, CODE_FOR_vashlv4si3, "spu_sl_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW, CODE_FOR_nothing, "spu_slqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SLQW_0, CODE_FOR_shlqbi_ti, "spu_slqw_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_1, CODE_FOR_shlqbi_ti, "spu_slqw_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
Index: gcc/config/spu/spu.md
===================================================================
--- gcc/config/spu/spu.md (revision 135303)
+++ gcc/config/spu/spu.md (revision 135304)
@@ -211,6 +211,9 @@ (define_mode_iterator VCMPU [V16QI
V8HI
V4SI])
+(define_mode_attr v [(V8HI "v") (V4SI "v")
+ (HI "") (SI "")])
+
(define_mode_attr bh [(QI "b") (V16QI "b")
(HI "h") (V8HI "h")
(SI "") (V4SI "")])
@@ -727,7 +730,7 @@ (define_insn_and_split "floatunssidf2_in
rtx op6_ti = gen_rtx_REG (TImode, REGNO (ops[6]));
emit_insn (gen_clzv4si2 (ops[3],op1_v4si));
emit_move_insn (ops[6], spu_const (V4SImode, 1023+31));
- emit_insn (gen_ashlv4si3 (ops[4],op1_v4si,ops[3]));
+ emit_insn (gen_vashlv4si3 (ops[4],op1_v4si,ops[3]));
emit_insn (gen_ceq_v4si (ops[5],ops[3],spu_const (V4SImode, 32)));
emit_insn (gen_subv4si3 (ops[6],ops[6],ops[3]));
emit_insn (gen_addv4si3 (ops[4],ops[4],ops[4]));
@@ -822,7 +825,7 @@ (define_insn_and_split "floatunsdidf2_in
rtx op4_df = gen_rtx_REG (DFmode, REGNO(ops[4]));
rtx op5_df = gen_rtx_REG (DFmode, REGNO(ops[5]));
emit_insn (gen_clzv4si2 (ops[4],op1_v4si));
- emit_insn (gen_ashlv4si3 (ops[5],op1_v4si,ops[4]));
+ emit_insn (gen_vashlv4si3 (ops[5],op1_v4si,ops[4]));
emit_insn (gen_ceq_v4si (ops[6],ops[4],spu_const (V4SImode, 32)));
emit_insn (gen_subv4si3 (ops[4],ops[3],ops[4]));
emit_insn (gen_addv4si3 (ops[5],ops[5],ops[5]));
@@ -1222,7 +1225,7 @@ (define_expand "mulv8hi3"
emit_move_insn (mask, spu_const (V4SImode, 0x0000ffff));
emit_insn (gen_spu_mpyhh (high, operands[1], operands[2]));
emit_insn (gen_spu_mpy (low, operands[1], operands[2]));
- emit_insn (gen_ashlv4si3 (shift, high, spu_const(V4SImode, 16)));
+ emit_insn (gen_vashlv4si3 (shift, high, spu_const(V4SImode, 16)));
emit_insn (gen_selb (result, shift, low, mask));
DONE;
}")
@@ -2100,9 +2103,9 @@ (define_insn "sumb_si"
[(set_attr "type" "fxb")])
-;; ashl
+;; ashl, vashl
-(define_insn "ashl<mode>3"
+(define_insn "<v>ashl<mode>3"
[(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r")
(ashift:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r")
(match_operand:VHSI 2 "spu_nonmem_operand" "r,W")))]
@@ -2234,9 +2237,9 @@ (define_insn "shlqby_ti"
[(set_attr "type" "shuf,shuf")])
-;; lshr
+;; lshr, vlshr
-(define_insn_and_split "lshr<mode>3"
+(define_insn_and_split "<v>lshr<mode>3"
[(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r")
(lshiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r")
(match_operand:VHSI 2 "spu_nonmem_operand" "r,W")))
@@ -2363,9 +2366,9 @@ (define_insn "rotqmby_<mode>"
[(set_attr "type" "shuf")])
-;; ashr
+;; ashr, vashr
-(define_insn_and_split "ashr<mode>3"
+(define_insn_and_split "<v>ashr<mode>3"
[(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r")
(ashiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r")
(match_operand:VHSI 2 "spu_nonmem_operand" "r,W")))
@@ -2430,7 +2433,7 @@ (define_insn_and_split "ashrdi3"
emit_insn (gen_lshrti3 (op0, op1, GEN_INT (32)));
emit_insn (gen_spu_xswd (op0d, op0v));
if (val > 32)
- emit_insn (gen_ashrv4si3 (op0v, op0v, spu_const (V4SImode, val - 32)));
+ emit_insn (gen_vashrv4si3 (op0v, op0v, spu_const (V4SImode, val - 32)));
}
else
{
@@ -2479,7 +2482,7 @@ (define_expand "ashrti3"
rtx op1_v4si = spu_gen_subreg (V4SImode, operands[1]);
rtx t = gen_reg_rtx (TImode);
emit_insn (gen_subsi3 (sign_shift, GEN_INT (128), force_reg (SImode, operands[2])));
- emit_insn (gen_ashrv4si3 (sign_mask_v4si, op1_v4si, spu_const (V4SImode, 31)));
+ emit_insn (gen_vashrv4si3 (sign_mask_v4si, op1_v4si, spu_const (V4SImode, 31)));
emit_insn (gen_fsm_ti (sign_mask, sign_mask));
emit_insn (gen_ashlti3 (sign_mask, sign_mask, sign_shift));
emit_insn (gen_lshrti3 (t, operands[1], operands[2]));
@@ -2496,9 +2499,9 @@ (define_insn "fsm_ti"
[(set_attr "type" "shuf")])
-;; rotl
+;; vrotl, rotl
-(define_insn "rotl<mode>3"
+(define_insn "<v>rotl<mode>3"
[(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r")
(rotate:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r")
(match_operand:VHSI 2 "spu_nonmem_operand" "r,W")))]
@@ -3046,14 +3049,14 @@ (define_expand "cgt_df"
emit_insn (gen_iorv4si3 (a_nan, a_nan, b_nan));
}
emit_move_insn (zero, CONST0_RTX (V4SImode));
- emit_insn (gen_ashrv4si3 (asel, ra, spu_const (V4SImode, 31)));
+ emit_insn (gen_vashrv4si3 (asel, ra, spu_const (V4SImode, 31)));
emit_insn (gen_shufb (asel, asel, asel, hi_promote));
emit_insn (gen_bg_v4si (abor, zero, a_abs));
emit_insn (gen_shufb (abor, abor, abor, borrow_shuffle));
emit_insn (gen_sfx_v4si (abor, zero, a_abs, abor));
emit_insn (gen_selb (abor, a_abs, abor, asel));
- emit_insn (gen_ashrv4si3 (bsel, rb, spu_const (V4SImode, 31)));
+ emit_insn (gen_vashrv4si3 (bsel, rb, spu_const (V4SImode, 31)));
emit_insn (gen_shufb (bsel, bsel, bsel, hi_promote));
emit_insn (gen_bg_v4si (bbor, zero, b_abs));
emit_insn (gen_shufb (bbor, bbor, bbor, borrow_shuffle));
@@ -3154,13 +3157,13 @@ (define_expand "cgt_v2df"
emit_insn (gen_shufb (b_nan, b_nan, b_nan, hi_promote));
emit_insn (gen_iorv4si3 (a_nan, a_nan, b_nan));
emit_move_insn (zero, CONST0_RTX (V4SImode));
- emit_insn (gen_ashrv4si3 (asel, ra, spu_const (V4SImode, 31)));
+ emit_insn (gen_vashrv4si3 (asel, ra, spu_const (V4SImode, 31)));
emit_insn (gen_shufb (asel, asel, asel, hi_promote));
emit_insn (gen_bg_v4si (abor, zero, a_abs));
emit_insn (gen_shufb (abor, abor, abor, borrow_shuffle));
emit_insn (gen_sfx_v4si (abor, zero, a_abs, abor));
emit_insn (gen_selb (abor, a_abs, abor, asel));
- emit_insn (gen_ashrv4si3 (bsel, rb, spu_const (V4SImode, 31)));
+ emit_insn (gen_vashrv4si3 (bsel, rb, spu_const (V4SImode, 31)));
emit_insn (gen_shufb (bsel, bsel, bsel, hi_promote));
emit_insn (gen_bg_v4si (bbor, zero, b_abs));
emit_insn (gen_shufb (bbor, bbor, bbor, borrow_shuffle));
@@ -3344,7 +3347,7 @@ (define_expand "dftsv"
0x08090A0B, 0x08090A0B);
emit_move_insn (hi_promote, pat);
- emit_insn (gen_ashrv4si3 (sign, ra, spu_const (V4SImode, 31)));
+ emit_insn (gen_vashrv4si3 (sign, ra, spu_const (V4SImode, 31)));
emit_insn (gen_shufb (sign, sign, sign, hi_promote));
emit_insn (gen_andv4si3 (abs, ra, sign_mask));
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 135303)
+++ gcc/config/rs6000/rs6000.c (revision 135304)
@@ -7109,20 +7109,20 @@ static struct builtin_description bdesc_
{ MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
- { MASK_ALTIVEC, CODE_FOR_ashlv16qi3, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
- { MASK_ALTIVEC, CODE_FOR_ashlv8hi3, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
- { MASK_ALTIVEC, CODE_FOR_ashlv4si3, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
+ { MASK_ALTIVEC, CODE_FOR_vashlv16qi3, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
+ { MASK_ALTIVEC, CODE_FOR_vashlv8hi3, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
+ { MASK_ALTIVEC, CODE_FOR_vashlv4si3, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
{ MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
- { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
- { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
- { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
- { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
- { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
- { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
+ { MASK_ALTIVEC, CODE_FOR_vlshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
+ { MASK_ALTIVEC, CODE_FOR_vlshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
+ { MASK_ALTIVEC, CODE_FOR_vlshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
+ { MASK_ALTIVEC, CODE_FOR_vashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
+ { MASK_ALTIVEC, CODE_FOR_vashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
+ { MASK_ALTIVEC, CODE_FOR_vashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
{ MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
Index: gcc/config/rs6000/altivec.md
===================================================================
--- gcc/config/rs6000/altivec.md (revision 135303)
+++ gcc/config/rs6000/altivec.md (revision 135304)
@@ -575,7 +575,7 @@ (define_expand "mulv4sf3"
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
neg0 = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
- emit_insn (gen_ashlv4si3 (neg0, neg0, neg0));
+ emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
/* Use the multiply-add. */
emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
@@ -634,7 +634,7 @@ (define_expand "mulv4si3"
high_product = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
- emit_insn (gen_ashlv4si3 (high_product, high_product, sixteen));
+ emit_insn (gen_vashlv4si3 (high_product, high_product, sixteen));
emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
@@ -1238,7 +1238,7 @@ (define_insn "altivec_vslo"
"vslo %0,%1,%2"
[(set_attr "type" "vecperm")])
-(define_insn "ashl<mode>3"
+(define_insn "vashl<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
(ashift:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v") ))]
@@ -1246,7 +1246,7 @@ (define_insn "ashl<mode>3"
"vsl %0,%1,%2"
[(set_attr "type" "vecsimple")])
-(define_insn "lshr<mode>3"
+(define_insn "vlshr<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
(lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v") ))]
@@ -1254,7 +1254,7 @@ (define_insn "lshr<mode>3"
"vsr %0,%1,%2"
[(set_attr "type" "vecsimple")])
-(define_insn "ashr<mode>3"
+(define_insn "vashr<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
(ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v") ))]
@@ -2640,7 +2640,7 @@ (define_expand "negv4sf2"
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
neg0 = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
- emit_insn (gen_ashlv4si3 (neg0, neg0, neg0));
+ emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
/* XOR */
emit_insn (gen_xorv4sf3 (operands[0],
++++++ gcc-4.3.2-20080715.tar.bz2 -> gcc-4.3.2-20080806.tar.bz2 ++++++
gcc43/gcc-4.3.2-20080715.tar.bz2 /mounts/work_src_done/STABLE/gcc43/gcc-4.3.2-20080806.tar.bz2 differ: byte 11, line 1
++++++ gcc.spec.in ++++++
--- gcc43/gcc.spec.in 2008-07-17 17:46:42.000000000 +0200
+++ /mounts/work_src_done/STABLE/gcc43/gcc.spec.in 2008-08-06 14:41:52.000000000 +0200
@@ -122,7 +122,7 @@
URL: http://gcc.gnu.org/
License: GPL
-Version: 4.3.2_20080715
+Version: 4.3.2_20080806
Release: 1
%define gcc_version %(echo %version | sed 's/_.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -167,6 +167,8 @@
Patch30: Wunprototyped-calls.diff
Patch31: pr27799.diff
Patch39: pr36343.diff
+Patch40: pr36765.diff
+Patch41: pr36613.diff
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -180,6 +182,11 @@
Patch72: pr34043-3.diff
Patch73: pr34043-4.diff
Patch74: pr34043-5.diff
+Patch75: amd-SSE5-shift-ppc-1.diff
+Patch76: amd-SSE5-shift-ppc-2.diff
+Patch77: amd-SSE5-shift.diff
+Patch78: amd-cunroll-1.diff
+Patch79: amd-cunroll-2.diff
# Patches for Intel features
Patch80: intel303993-aes.diff
# Patches for IBM features
@@ -192,6 +199,9 @@
Patch96: pr36745.diff
Patch97: pr36822.diff
Patch98: ibm-mpower4.diff
+Patch99: ibm-vector-keyword-1
+Patch100: ibm-vector-keyword-2
+Patch101: ibm-vector-keyword-3
# LIBJAVA-DELETE-BEGIN
%description
@@ -830,6 +840,8 @@
%patch30
%patch31
%patch39
+%patch40
+%patch41
%patch51
%patch55
%patch57
@@ -840,6 +852,11 @@
%patch72
%patch73
%patch74 -p1
+%patch75
+%patch76
+%patch77
+%patch78
+%patch79
%patch80
%patch90
%patch91
@@ -850,6 +867,9 @@
%patch96
%patch97
#%patch98
+%patch99
+%patch100
+%patch101
%build
# Avoid rebuilding of generated files
@@ -1026,7 +1046,6 @@
--with-long-double-128 \
%endif
%if "%{TARGET_ARCH}" == "powerpc64"
- --with-cpu=default64 \
--enable-secureplt \
--with-long-double-128 \
%endif
@@ -1062,6 +1081,8 @@
mv %{GCCDIST}/libstdc++-v3/testsuite/libstdc++.log %{GCCDIST}/libstdc++-v3/testsuite/libstdc++-abi.log
mv %{GCCDIST}/libstdc++-v3/testsuite/libstdc++.sum %{GCCDIST}/libstdc++-v3/testsuite/libstdc++-abi.sum
make -k check $PARALLEL || true
+mkdir ../testresults
+../contrib/test_summary > ../testresults/test_summary.txt
%endif
%install
@@ -1262,7 +1283,6 @@
done
%if %{run_tests}
-mkdir ../testresults
cp `find . -name "*.sum"` ../testresults/
cp `find . -name "*.log" \! -name "config.log" |grep -v 'acats/tests' ` ../testresults/
chmod 644 ../testresults/*
@@ -1957,6 +1977,7 @@
%if %{run_tests}
%files -n gcc@base_ver@-testresults
%defattr(-,root,root)
+%doc testresults/test_summary.txt
%doc testresults/*.sum
%doc testresults/*.log
%endif
++++++ ibm-vector-keyword-1 ++++++
++++ 705 lines (skipped)
++++++ ibm-vector-keyword-2 ++++++
2008-07-24 Ben Elliston
* config/rs6000/rs6000-c.c: Move GTY(()) markers to match
conventional usage.
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c (revision 138103)
+++ gcc/config/rs6000/rs6000-c.c (revision 138104)
@@ -85,12 +85,12 @@ rs6000_pragma_longcall (cpp_reader *pfil
#define builtin_assert(TXT) cpp_assert (pfile, TXT)
/* Keep the AltiVec keywords handy for fast comparisons. */
-static tree __vector_keyword;
-static tree vector_keyword;
-static tree __pixel_keyword;
-static tree pixel_keyword;
-static tree __bool_keyword;
-static tree bool_keyword;
+static GTY(()) tree __vector_keyword;
+static GTY(()) tree vector_keyword;
+static GTY(()) tree __pixel_keyword;
+static GTY(()) tree pixel_keyword;
+static GTY(()) tree __bool_keyword;
+static GTY(()) tree bool_keyword;
/* Preserved across calls. */
static tree expand_bool_pixel;
++++++ ibm-vector-keyword-3 ++++++
2008-07-24 Ben Elliston
* config/spu/spu-c.c (__vector_keyword): New variable.
(vector_keyword): Likewise.
(spu_categorize_keyword): New function.
(spu_macro_to_expand): Likewise.
(spu_cpu_cpp_builtins): Enable context-sensitive macros if not
compiling an ISO C dialect.
2008-07-24 Ben Elliston
* gcc.target/spu/vector.c: New test.
* gcc.target/spu/vector-ansi.c: Likewise.
Index: gcc/testsuite/gcc.target/spu/vector.c
===================================================================
--- gcc/testsuite/gcc.target/spu/vector.c (revision 0)
+++ gcc/testsuite/gcc.target/spu/vector.c (revision 138106)
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+#ifndef __VECTOR_KEYWORD_SUPPORTED__
+#error __VECTOR_KEYWORD_SUPPORTED__ is not defined
+#endif
+
+/* __vector is expanded unconditionally. */
+__vector int vi;
+__vector unsigned char vuc;
+__vector signed char vsc;
+__vector unsigned short vus;
+__vector signed short vss;
+__vector unsigned int vui;
+__vector signed int vsi;
+__vector unsigned long long ull;
+__vector signed long long sll;
+__vector float vf;
+__vector double vd;
+
+/* vector is expanded conditionally, based on the context. */
+vector int vi;
+vector unsigned char vuc;
+vector signed char vsc;
+vector unsigned short vus;
+vector signed short vss;
+vector unsigned int vui;
+vector signed int vsi;
+vector unsigned long long ull;
+vector signed long long sll;
+vector float vf;
+vector double vd;
Index: gcc/testsuite/gcc.target/spu/vector-ansi.c
===================================================================
--- gcc/testsuite/gcc.target/spu/vector-ansi.c (revision 0)
+++ gcc/testsuite/gcc.target/spu/vector-ansi.c (revision 138106)
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-ansi" } */
+
+/* This is done by spu_internals.h, but we not include it here to keep
+ down the dependencies. */
+
+#ifndef __VECTOR_KEYWORD_SUPPORTED__
+#define vector __vector
+#endif
+
+/* __vector is expanded unconditionally by the preprocessor. */
+__vector int vi;
+__vector unsigned char vuc;
+__vector signed char vsc;
+__vector unsigned short vus;
+__vector signed short vss;
+__vector unsigned int vui;
+__vector signed int vsi;
+__vector unsigned long long ull;
+__vector signed long long sll;
+__vector float vf;
+__vector double vd;
+
+/* vector is expanded by the define above, regardless of context. */
+vector int vi;
+vector unsigned char vuc;
+vector signed char vsc;
+vector unsigned short vus;
+vector signed short vss;
+vector unsigned int vui;
+vector signed int vsi;
+vector unsigned long long ull;
+vector signed long long sll;
+vector float vf;
+vector double vd;
Index: gcc/config/spu/spu-c.c
===================================================================
--- gcc/config/spu/spu-c.c (revision 138105)
+++ gcc/config/spu/spu-c.c (revision 138106)
@@ -35,6 +35,64 @@
#include "spu-builtins.h"
+/* Keep the vector keywords handy for fast comparisons. */
+static GTY(()) tree __vector_keyword;
+static GTY(()) tree vector_keyword;
+
+static cpp_hashnode *
+spu_categorize_keyword (const cpp_token *tok)
+{
+ if (tok->type == CPP_NAME)
+ {
+ cpp_hashnode *ident = tok->val.node;
+
+ if (ident == C_CPP_HASHNODE (vector_keyword)
+ || ident == C_CPP_HASHNODE (__vector_keyword))
+ return C_CPP_HASHNODE (__vector_keyword);
+ else
+ return ident;
+ }
+ return 0;
+}
+
+/* Called to decide whether a conditional macro should be expanded.
+ Since we have exactly one such macro (i.e, 'vector'), we do not
+ need to examine the 'tok' parameter. */
+
+static cpp_hashnode *
+spu_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
+{
+ cpp_hashnode *expand_this = tok->val.node;
+ cpp_hashnode *ident;
+
+ ident = spu_categorize_keyword (tok);
+ if (ident == C_CPP_HASHNODE (__vector_keyword))
+ {
+ tok = cpp_peek_token (pfile, 0);
+ ident = spu_categorize_keyword (tok);
+
+ if (ident)
+ {
+ enum rid rid_code = (enum rid)(ident->rid_code);
+ if (ident->type == NT_MACRO)
+ {
+ (void) cpp_get_token (pfile);
+ tok = cpp_peek_token (pfile, 0);
+ ident = spu_categorize_keyword (tok);
+ if (ident)
+ rid_code = (enum rid)(ident->rid_code);
+ }
+
+ if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
+ || rid_code == RID_SHORT || rid_code == RID_SIGNED
+ || rid_code == RID_INT || rid_code == RID_CHAR
+ || rid_code == RID_FLOAT || rid_code == RID_DOUBLE)
+ expand_this = C_CPP_HASHNODE (__vector_keyword);
+ }
+ }
+ return expand_this;
+}
+
/* target hook for resolve_overloaded_builtin(). Returns a function call
RTX if we can resolve the overloaded builtin */
tree
@@ -140,6 +198,22 @@ spu_cpu_cpp_builtins (struct cpp_reader
if (spu_arch == PROCESSOR_CELLEDP)
builtin_define_std ("__SPU_EDP__");
builtin_define_std ("__vector=__attribute__((__spu_vector__))");
+
+ if (!flag_iso)
+ {
+ /* Define this when supporting context-sensitive keywords. */
+ cpp_define (pfile, "__VECTOR_KEYWORD_SUPPORTED__");
+ cpp_define (pfile, "vector=vector");
+
+ /* Initialize vector keywords. */
+ __vector_keyword = get_identifier ("__vector");
+ C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
+ vector_keyword = get_identifier ("vector");
+ C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
+
+ /* Enable context-sensitive macros. */
+ cpp_get_callbacks (pfile)->macro_to_expand = spu_macro_to_expand;
+ }
}
void
++++++ pr36613.diff ++++++
Hi,
reload has a problem when it tries to reuse (not to be confused with
inheriting) a reload with a different mode. In the problematic case at
hand we first find a SImode reload of %ecx to %edx (using %ecx as
reload_reg), and try to fit a second reload from %cl to %dl into that.
This is quite fine, just that the merging of both reloads overwrites the
in/out members, and leaves us with a QImode reload. Or better, it merges
the inmode/outmode (depending on size, i.e. leaves the larger), but
overwrites the reload operands itself.
So we are left with a SImode reload dealing with %cl and %dl.
Unfortunately do_input_reload (and do_output_reload) don't care that much
for inmode/outmode (which would be correct here), but rather simply take
what is noted in in/out. So we emit a QImode move, thereby not correctly
emitting the insns for the first reload.
As I noted in the large bugzilla comment I see two ways of fixing this:
1) also take the size of operands into account while merging the in/out
members, in push_reload
2) overhaul do_input_reload and do_output_reload to care for
inmode/outmode _first_ before falling back to the operands.
Option (2) is more complicated as it potentially requires adjusting the
RTXes we find in in/out for the mode we want. There's also a large scary
comment at do_input_reload speculating about all kinds of potential
breakages, it's very old and probably half of the fear in there doesn't
apply anymore, but I didn't feel like poking into 20 year old history to
see why and how it mattered exactly. I think the whole comment is mood
when we rely on inmode/outmode, but in the end I only did (1), found it to
fix the testcase and regstrapped this successfully on i686 and x86_64.
Since that I somewhat changed the patch, so I'm currently regstrapping it
again. Okay for trunk if that passes? At least 4.3 needs that too,
eventually. If someone also wants to test this on 4.2 I would be glad.
Ciao,
Michael.
PR target/36613
* reload.c (push_reload): Merge in,out,in_reg,out_reg members
for reused reload, instead of overwriting them.
* gcc.target/i386/pr36613.c: New testcase.
Index: gcc/reload.c
===================================================================
*** gcc/reload.c (revision 137652)
--- gcc/reload.c (working copy)
*************** push_reload (rtx in, rtx out, rtx *inloc
*** 1403,1415 ****
else
remove_address_replacements (rld[i].in);
}
! rld[i].in = in;
! rld[i].in_reg = in_reg;
}
if (out != 0)
{
! rld[i].out = out;
! rld[i].out_reg = outloc ? *outloc : 0;
}
if (reg_class_subset_p (class, rld[i].class))
rld[i].class = class;
--- 1403,1438 ----
else
remove_address_replacements (rld[i].in);
}
! /* When emitting reloads we don't necessarily look at the in-
! and outmode, but also directly at the operands (in and out).
! So we can't simply overwrite them with whatever we have found
! for this (to-be-merged) reload, we have to "merge" that too.
! Reusing another reload already verified that we deal with the
! same operands, just possibly in different modes. So we
! overwrite the operands only when the new mode is larger.
! See also PR33613. */
! if (!rld[i].in
! || GET_MODE_SIZE (GET_MODE (in))
! > GET_MODE_SIZE (GET_MODE (rld[i].in)))
! rld[i].in = in;
! if (!rld[i].in_reg
! || (in_reg
! && GET_MODE_SIZE (GET_MODE (in_reg))
! > GET_MODE_SIZE (GET_MODE (rld[i].in_reg))))
! rld[i].in_reg = in_reg;
}
if (out != 0)
{
! if (!rld[i].out
! || (out
! && GET_MODE_SIZE (GET_MODE (out))
! > GET_MODE_SIZE (GET_MODE (rld[i].out))))
! rld[i].out = out;
! if (outloc
! && (!rld[i].out_reg
! || GET_MODE_SIZE (GET_MODE (*outloc))
! > GET_MODE_SIZE (GET_MODE (rld[i].out_reg))))
! rld[i].out_reg = *outloc;
}
if (reg_class_subset_p (class, rld[i].class))
rld[i].class = class;
++++++ pr36765.diff ++++++
2008-07-11 Richard Guenther
PR tree-optimization/36765
* tree-ssa-alias.c (compute_flow_insensitive_aliasing): Add
aliases from HEAP vars to SMTs.
* gcc.c-torture/execute/pr36765.c: New testcase.
Index: gcc/tree-ssa-alias.c
===================================================================
*** gcc/tree-ssa-alias.c (revision 137712)
--- gcc/tree-ssa-alias.c (working copy)
*************** have_common_aliases_p (bitmap tag1aliase
*** 2370,2375 ****
--- 2370,2377 ----
static void
compute_flow_insensitive_aliasing (struct alias_info *ai)
{
+ referenced_var_iterator rvi;
+ tree var;
size_t i;
timevar_push (TV_FLOW_INSENSITIVE);
*************** compute_flow_insensitive_aliasing (struc
*** 2460,2465 ****
--- 2462,2485 ----
add_may_alias (tag1, tag2);
}
}
+
+ /* We have to add all HEAP variables to all SMTs aliases bitmaps.
+ As we don't know which effective type the HEAP will have we cannot
+ do better here and we need the conflicts with obfuscated pointers
+ (a simple (*(int[n] *)ptr)[i] will do, with ptr from a VLA array
+ allocation). */
+ for (i = 0; i < ai->num_pointers; i++)
+ {
+ struct alias_map_d *p_map = ai->pointers[i];
+ tree tag = symbol_mem_tag (p_map->var);
+
+ FOR_EACH_REFERENCED_VAR (var, rvi)
+ {
+ if (var_ann (var)->is_heapvar)
+ add_may_alias (tag, var);
+ }
+ }
+
timevar_pop (TV_FLOW_INSENSITIVE);
}
Index: gcc/testsuite/gcc.c-torture/execute/pr36765.c
===================================================================
*** gcc/testsuite/gcc.c-torture/execute/pr36765.c (revision 0)
--- gcc/testsuite/gcc.c-torture/execute/pr36765.c (revision 0)
***************
*** 0 ****
--- 1,15 ----
+ int __attribute__((noinline))
+ foo(int i)
+ {
+ int *p = __builtin_malloc (4 * sizeof(int));
+ *p = 0;
+ p[i] = 1;
+ return *p;
+ }
+ extern void abort (void);
+ int main()
+ {
+ if (foo(0) != 1)
+ abort ();
+ return 0;
+ }
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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