Hello community,
here is the log from the commit of package coreboot-utils
checked in at Wed Mar 19 01:47:56 CET 2008.
--------
--- arch/i386/coreboot-utils/coreboot-utils.changes 2008-01-21 08:34:30.000000000 +0100
+++ /mounts/work_src_done/STABLE/coreboot-utils/coreboot-utils.changes 2008-03-17 17:15:47.000000000 +0100
@@ -1,0 +2,7 @@
+Mon Mar 17 17:14:59 CET 2008 - bwalle@suse.de
+
+- rename lxbios to nvramtool
+- update nvramtool to svn release r3124
+- update flashrom to svn release r3153
+
+-------------------------------------------------------------------
Old:
----
flashrom-svn-r3061.tar.bz2
lxbios-svn-r3058.tar.bz2
New:
----
flashrom-svn-r3153.tar.bz2
nvramtool-svn-r3124.tar.bz2
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ coreboot-utils.spec ++++++
--- /var/tmp/diff_new_pack.g15710/_old 2008-03-19 01:47:50.000000000 +0100
+++ /var/tmp/diff_new_pack.g15710/_new 2008-03-19 01:47:50.000000000 +0100
@@ -1,5 +1,5 @@
#
-# spec file for package coreboot-utils (Version r3061)
+# spec file for package coreboot-utils (Version r3153)
#
# Copyright (c) 2008 SUSE LINUX Products GmbH, Nuernberg, Germany.
# This file and all modifications and additions to the pristine
@@ -10,16 +10,17 @@
# norootforbuild
+
Name: coreboot-utils
Url: http://linuxbios.org/
Summary: A universal flash programming utility
-Version: r3061
+Version: r3153
Release: 1
-%define lxbios_version r3058
+%define nvramtool_version r3124
License: GPL v2 only; GPL v2 or later
Group: Development/Tools/Other
Source0: flashrom-svn-%{version}.tar.bz2
-Source1: lxbios-svn-%{lxbios_version}.tar.bz2
+Source1: nvramtool-svn-%{nvramtool_version}.tar.bz2
BuildRoot: %{_tmppath}/%{name}-%{version}-build
BuildRequires: pciutils-devel zlib-devel
Provides: flashrom = %{version}
@@ -46,7 +47,7 @@
CFLAGS="$RPM_OPT_FLAGS -Os -Wall -DDISABLE_DOC " \
LDFLAGS="-lpci -lz"
gzip flashrom.8
-cd lxbios-svn-%{lxbios_version}
+cd nvramtool-svn-%{nvramtool_version}
make %{?jobs:-j%jobs} \
CFLAGS="$RPM_OPT_FLAGS -Os -Wall -DDISABLE_DOC " \
LDFLAGS="-lpci -lz"
@@ -58,15 +59,15 @@
mkdir -p $RPM_BUILD_ROOT/%{_mandir}/man8
install -m 0755 flashrom $RPM_BUILD_ROOT/%{_sbindir}
install -m 0644 flashrom.8.gz $RPM_BUILD_ROOT/%{_mandir}/man8
-cd lxbios-svn-%{lxbios_version}
-install -m 0755 lxbios $RPM_BUILD_ROOT/%{_bindir}
-install -m 0644 lxbios.1.gz $RPM_BUILD_ROOT/%{_mandir}/man1
+cd nvramtool-svn-%{nvramtool_version}
+install -m 0755 nvramtool $RPM_BUILD_ROOT/%{_bindir}
+install -m 0644 nvramtool.1.gz $RPM_BUILD_ROOT/%{_mandir}/man1
cd -
cp README README.flashrom
-cp lxbios-svn-%{lxbios_version}/COPYING .
-cp lxbios-svn-%{lxbios_version}/DISCLAIMER DISCLAIMER.lxbios
-cp lxbios-svn-%{lxbios_version}/README README.lxbios
-cp lxbios-svn-%{lxbios_version}/ChangeLog ChangeLog.lxbios
+cp nvramtool-svn-%{nvramtool_version}/COPYING .
+cp nvramtool-svn-%{nvramtool_version}/DISCLAIMER DISCLAIMER.nvramtool
+cp nvramtool-svn-%{nvramtool_version}/README README.nvramtool
+cp nvramtool-svn-%{nvramtool_version}/ChangeLog ChangeLog.nvramtool
%clean
rm -rf %{buildroot}
@@ -75,13 +76,17 @@
%defattr(-,root,root)
%doc COPYING
%doc README.flashrom
-%doc DISCLAIMER.lxbios ChangeLog.lxbios README.lxbios
+%doc DISCLAIMER.nvramtool ChangeLog.nvramtool README.nvramtool
%{_sbindir}/flashrom
-%{_bindir}/lxbios
-%{_mandir}/man1/lxbios.1.gz
+%{_bindir}/nvramtool
+%{_mandir}/man1/nvramtool.1.gz
%{_mandir}/man8/flashrom.8.gz
%changelog
+* Mon Mar 17 2008 bwalle@suse.de
+- rename lxbios to nvramtool
+- update nvramtool to svn release r3124
+- update flashrom to svn release r3153
* Sun Jan 20 2008 bwalle@suse.de
- update to svn release r3061
o Support SPI flash chips bigger than 512 kByte sitting behind
++++++ flashrom-svn-r3061.tar.bz2 -> flashrom-svn-r3153.tar.bz2 ++++++
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/board_enable.c new/flashrom-svn-r3153/board_enable.c
--- old/flashrom-svn-r3061/board_enable.c 2008-01-18 16:33:10.000000000 +0100
+++ new/flashrom-svn-r3153/board_enable.c 2008-03-13 19:41:07.000000000 +0100
@@ -3,7 +3,7 @@
*
* Copyright (C) 2005-2007 coresystems GmbH
* Copyright (C) 2006 Uwe Hermann
- * Copyright (C) 2007 Luc Verhaegen
+ * Copyright (C) 2007-2008 Luc Verhaegen
* Copyright (C) 2007 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "flash.h"
/*
@@ -213,6 +214,28 @@
}
/**
+ * Suited for VIAs EPIA SP.
+ */
+static int board_via_epia_sp(const char *name)
+{
+ struct pci_dev *dev;
+ uint8_t val;
+
+ dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
+ if (!dev) {
+ fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
+ return -1;
+ }
+
+ /* All memory cycles, not just ROM ones, go to LPC */
+ val = pci_read_byte(dev, 0x59);
+ val &= ~0x80;
+ pci_write_byte(dev, 0x59, val);
+
+ return 0;
+}
+
+/**
* Suited for ASUS P5A.
*
* This is rather nasty code, but there's no way to do this cleanly.
@@ -346,12 +369,77 @@
}
/**
+ * Suited for Artec Group DBE61 and DBE62.
+ */
+static int board_artecgroup_dbe6x(const char *name)
+{
+#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
+#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
+#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
+#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
+#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
+#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
+#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
+#define DBE6x_BOOT_LOC_FLASH (2)
+#define DBE6x_BOOT_LOC_FWHUB (3)
+
+ unsigned long msr[2];
+ int msr_fd;
+ unsigned long boot_loc;
+
+ msr_fd = open("/dev/cpu/0/msr", O_RDWR);
+ if (msr_fd == -1) {
+ perror("open /dev/cpu/0/msr");
+ return -1;
+ }
+
+ if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) {
+ perror("lseek");
+ close(msr_fd);
+ return -1;
+ }
+
+ if (read(msr_fd, (void*) msr, 8) != 8) {
+ perror("read");
+ close(msr_fd);
+ return -1;
+ }
+
+ if ((msr[0] & (DBE6x_BOOT_OP_LATCHED)) ==
+ (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
+ boot_loc = DBE6x_BOOT_LOC_FWHUB;
+ else
+ boot_loc = DBE6x_BOOT_LOC_FLASH;
+
+ msr[0] &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
+ msr[0] |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
+ (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
+
+ if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) {
+ perror("lseek");
+ close(msr_fd);
+ return -1;
+ }
+
+ if (write(msr_fd, (void*) msr, 8) != 8) {
+ perror("write");
+ close(msr_fd);
+ return -1;
+ }
+
+ close(msr_fd);
+ return 0;
+}
+
+/**
* We use 2 sets of IDs here, you're free to choose which is which. This
* is to provide a very high degree of certainty when matching a board on
* the basis of subsystem/card IDs. As not every vendor handles
* subsystem/card IDs in a sane manner.
*
* Keep the second set NULLed if it should be ignored.
+ *
+ * Keep the subsystem IDs NULLed if they don't identify the board fully.
*/
struct board_pciid_enable {
/* Any device, but make it sensible, like the ISA bridge. */
@@ -393,6 +481,8 @@
NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m},
{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx},
+ {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01,
+ NULL, NULL, "VIA EPIA SP", board_via_epia_sp},
{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498,
NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx},
{0x10B9, 0x1541, 0x0000, 0x0000, 0x10B9, 0x1533, 0x0000, 0x0000,
@@ -403,9 +493,33 @@
"epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3},
{0x8086, 0x1130, 0x0000, 0x0000, 0x105a, 0x0d30, 0x105a, 0x4d33,
"acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd},
+ {0x1022, 0x2090, 0x0000, 0x0000, 0x1022, 0x2080, 0x0000, 0x0000,
+ "artecgroup", "dbe61", "Artec Group DBE61", board_artecgroup_dbe6x},
+ {0x1022, 0x2090, 0x0000, 0x0000, 0x1022, 0x2080, 0x0000, 0x0000,
+ "artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x},
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */
};
+void print_supported_boards(void)
+{
+ int i;
+
+ printf("\nSupported mainboards (this list is not exhaustive!):\n\n");
+
+ for (i = 0; board_pciid_enables[i].name != NULL; i++) {
+ if (board_pciid_enables[i].lb_vendor != NULL) {
+ printf("%s (-m %s:%s)\n", board_pciid_enables[i].name,
+ board_pciid_enables[i].lb_vendor,
+ board_pciid_enables[i].lb_part);
+ } else {
+ printf("%s (autodetected)\n",
+ board_pciid_enables[i].name);
+ }
+ }
+
+ printf("\nSee also: http://coreboot.org/Flashrom\n");
+}
+
/**
* Match boards on coreboot table gathered vendor and part name.
* Require main PCI IDs to match too as extra safety.
@@ -413,9 +527,10 @@
static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, const char *part)
{
struct board_pciid_enable *board = board_pciid_enables;
+ struct board_pciid_enable *partmatch = NULL;
for (; board->name; board++) {
- if (!board->lb_vendor || strcmp(board->lb_vendor, vendor))
+ if (vendor && (!board->lb_vendor || strcmp(board->lb_vendor, vendor)))
continue;
if (!board->lb_part || strcmp(board->lb_part, part))
@@ -427,9 +542,24 @@
if (board->second_vendor &&
!pci_dev_find(board->second_vendor, board->second_device))
continue;
- return board;
+
+ if (vendor)
+ return board;
+
+ if (partmatch) {
+ /* a second entry has a matching part name */
+ printf("AMBIGUOUS BOARD NAME: %s\n", part);
+ printf("At least vendors '%s' and '%s' match.\n",
+ partmatch->lb_vendor, board->lb_vendor);
+ printf("Please use the full -m vendor:part syntax.\n");
+ return NULL;
+ }
+ partmatch = board;
}
+ if (partmatch)
+ return partmatch;
+
printf("NOT FOUND %s:%s\n", vendor, part);
return NULL;
@@ -477,7 +607,7 @@
struct board_pciid_enable *board = NULL;
int ret = 0;
- if (vendor && part)
+ if (part)
board = board_match_coreboot_name(vendor, part);
if (!board)
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/chipset_enable.c new/flashrom-svn-r3153/chipset_enable.c
--- old/flashrom-svn-r3061/chipset_enable.c 2007-12-04 22:49:06.000000000 +0100
+++ new/flashrom-svn-r3153/chipset_enable.c 2008-03-14 18:20:59.000000000 +0100
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
#include
#include "flash.h"
@@ -139,8 +140,8 @@
}
/*
- * See ie. page 375 of "Intel ICH7 External Design Specification"
- * http://download.intel.com/design/chipsets/datashts/30701302.pdf
+ * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
+ * http://download.intel.com/design/chipsets/datashts/30701303.pdf
*/
static int enable_flash_ich(struct pci_dev *dev, const char *name,
int bios_cntl)
@@ -153,6 +154,12 @@
*/
old = pci_read_byte(dev, bios_cntl);
+ printf_debug("BIOS Lock Enable: %sabled, ",
+ (old & (1 << 1)) ? "en" : "dis");
+ printf_debug("BIOS Write Enable: %sabled, ",
+ (old & (1 << 0)) ? "en" : "dis");
+ printf_debug("BIOS_CNTL is 0x%x\n", old);
+
new = old | 1;
if (new == old)
@@ -178,6 +185,50 @@
return enable_flash_ich(dev, name, 0xdc);
}
+static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name)
+{
+ uint8_t old, new, bbs;
+ uint32_t tmp, gcs;
+ void *rcba;
+
+ /* Root Complex Base Address Register (RCBA) */
+ tmp = pci_read_long(dev, 0xf0);
+ tmp &= 0xffffc000;
+ printf_debug("Root Complex Base Address Register = 0x%x\n", tmp);
+ rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp);
+ if (rcba == MAP_FAILED) {
+ perror("Can't mmap memory using " MEM_DEV);
+ exit(1);
+ }
+ printf_debug("GCS address = 0x%x\n", tmp + 0x3410);
+ gcs = *(volatile uint32_t *)(rcba + 0x3410);
+ printf_debug("GCS = 0x%x: ", gcs);
+ printf_debug("BIOS Interface Lock-Down: %sabled, ",
+ (gcs & 0x1) ? "en" : "dis");
+ bbs = (gcs >> 10) & 0x3;
+ printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs,
+ (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
+ printf_debug("SPIBAR = 0x%x\n", tmp + 0x3020);
+ /* TODO: Dump the SPI config regs */
+ munmap(rcba, 0x3510);
+
+ old = pci_read_byte(dev, 0xdc);
+ printf_debug("SPI Read Configuration: ");
+ new = (old >> 2) & 0x3;
+ switch (new) {
+ case 0:
+ case 1:
+ case 2:
+ printf_debug("prefetching %sabled, caching %sabled, ",
+ (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en");
+ break;
+ default:
+ printf_debug("invalid prefetching/caching settings, ");
+ break;
+ }
+ return enable_flash_ich_dc(dev, name);
+}
+
static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
{
uint8_t val;
@@ -226,51 +277,95 @@
return 0;
}
+/**
+ * Geode systems write protect the BIOS via RCONFs (cache settings similar
+ * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
+ * writing to MSRs, however requires instructions rdmsr/wrmsr, which are
+ * ring0 privileged instructions so only the kernel can do the read/write.
+ * This function, therefore, requires that the msr kernel module be loaded
+ * to access these instructions from user space using device /dev/cpu/0/msr.
+ *
+ * This hard-coded location could have potential problems on SMP machines
+ * since it assumes cpu0, but it is safe on the Geode which is not SMP.
+ *
+ * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
+ * To enable write to NOR Boot flash for the benefit of systems that have such
+ * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
+ *
+ * This is probably not portable beyond Linux.
+ */
static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
{
+ #define MSR_RCONF_DEFAULT 0x1808
+ #define MSR_NORF_CTL 0x51400018
+
int fd_msr;
unsigned char buf[8];
- unsigned int addr = 0x1808;
- /* Geode systems write protect the BIOS via RCONFs (cache
- * settings similar to MTRRs). To unlock, change MSR 0x1808
- * top byte to 0x22. Reading and writing to msr, however
- * requires instructions rdmsr/wrmsr, which are ring0 privileged
- * instructions so only the kernel can do the read/write. This
- * function, therefore, requires that the msr kernel module be
- * loaded to access these instructions from user space using
- * device /dev/cpu/0/msr. This hard-coded driver location
- * could have potential problems on SMP machines since it
- * assumes cpu0, but it is safe on the Geode which is not SMP.
- *
- * This is probably not portable beyond Linux.
- */
-
- fd_msr = open("/dev/cpu/0/msr", O_RDONLY);
+ fd_msr = open("/dev/cpu/0/msr", O_RDWR);
if (!fd_msr) {
perror("open msr");
return -1;
}
- lseek64(fd_msr, (off64_t) addr, SEEK_SET);
- read(fd_msr, buf, 8);
- close(fd_msr);
+
+ if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
+ perror("lseek64");
+ printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
+ close(fd_msr);
+ return -1;
+ }
+
+ if (read(fd_msr, buf, 8) != 8) {
+ perror("read msr");
+ close(fd_msr);
+ return -1;
+ }
+
if (buf[7] != 0x22) {
- printf("Enabling Geode MSR to write to flash.\n");
- buf[7] = 0x22;
- fd_msr = open("/dev/cpu/0/msr", O_WRONLY);
- if (!fd_msr) {
- perror("open msr");
+ buf[7] &= 0xfb;
+ if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
+ perror("lseek64");
+ close(fd_msr);
return -1;
}
- lseek64(fd_msr, (off64_t) addr, SEEK_SET);
+
if (write(fd_msr, buf, 8) < 0) {
perror("msr write");
- printf
- ("Cannot write to MSR. Make sure msr kernel is loaded: 'modprobe msr'\n");
+ close(fd_msr);
return -1;
}
+ }
+
+ if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
+ perror("lseek64");
+ close(fd_msr);
+ return -1;
+ }
+
+ if (read(fd_msr, buf, 8) != 8) {
+ perror("read msr");
+ close(fd_msr);
+ return -1;
+ }
+
+ /* Raise WE_CS3 bit. */
+ buf[0] |= 0x08;
+
+ if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
+ perror("lseek64");
close(fd_msr);
+ return -1;
}
+ if (write(fd_msr, buf, 8) < 0) {
+ perror("msr write");
+ close(fd_msr);
+ return -1;
+ }
+
+ close(fd_msr);
+
+ #undef MSR_RCONF_DEFAULT
+ #undef MSR_NORF_CTL
return 0;
}
@@ -466,57 +561,71 @@
} FLASH_ENABLE;
static const FLASH_ENABLE enables[] = {
- {0x1039, 0x0630, "SIS630", enable_flash_sis630},
- {0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4},
- {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
- {0x8086, 0x2410, "ICH", enable_flash_ich_4e},
- {0x8086, 0x2420, "ICH0", enable_flash_ich_4e},
- {0x8086, 0x2440, "ICH2", enable_flash_ich_4e},
- {0x8086, 0x244c, "ICH2-M", enable_flash_ich_4e},
- {0x8086, 0x2480, "ICH3-S", enable_flash_ich_4e},
- {0x8086, 0x248c, "ICH3-M", enable_flash_ich_4e},
- {0x8086, 0x24c0, "ICH4/ICH4-L", enable_flash_ich_4e},
- {0x8086, 0x24cc, "ICH4-M", enable_flash_ich_4e},
- {0x8086, 0x24d0, "ICH5/ICH5R", enable_flash_ich_4e},
- {0x8086, 0x2640, "ICH6/ICH6R", enable_flash_ich_dc},
- {0x8086, 0x2641, "ICH6-M", enable_flash_ich_dc},
- {0x8086, 0x27b0, "ICH7DH", enable_flash_ich_dc},
- {0x8086, 0x27b8, "ICH7/ICH7R", enable_flash_ich_dc},
- {0x8086, 0x27b9, "ICH7M", enable_flash_ich_dc},
- {0x8086, 0x27bd, "ICH7MDH", enable_flash_ich_dc},
- {0x8086, 0x2810, "ICH8/ICH8R", enable_flash_ich_dc},
- {0x8086, 0x2812, "ICH8DH", enable_flash_ich_dc},
- {0x8086, 0x2814, "ICH8DO", enable_flash_ich_dc},
- {0x1106, 0x8231, "VT8231", enable_flash_vt823x},
- {0x1106, 0x3177, "VT8235", enable_flash_vt823x},
- {0x1106, 0x3227, "VT8237", enable_flash_vt823x},
- {0x1106, 0x8324, "CX700", enable_flash_vt823x},
- {0x1106, 0x0686, "VT82C686", enable_flash_amd8111},
- {0x1078, 0x0100, "CS5530/CS5530A", enable_flash_cs5530},
- {0x100b, 0x0510, "SC1100", enable_flash_sc1100},
- {0x1039, 0x0008, "SIS5595", enable_flash_sis5595},
- {0x1022, 0x2080, "AMD GEODE CS5536", enable_flash_cs5536},
- {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
- {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
- {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
- {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
- {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */
- {0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804},
- {0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804},
- {0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804},
- {0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804},
- {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI-S4 */
- {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
- {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
- {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
- {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
- {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
- {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
- {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
- {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
- {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
+ {0x1039, 0x0630, "SiS630", enable_flash_sis630},
+ {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
+ {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
+ {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
+ {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e},
+ {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e},
+ {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e},
+ {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e},
+ {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e},
+ {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e},
+ {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e},
+ {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e},
+ {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
+ {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
+ {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi},
+ {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi},
+ {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi},
+ {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi},
+ {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi},
+ {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich_dc_spi},
+ {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi},
+ {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi},
+ {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich_dc_spi},
+ {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
+ {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
+ {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
+ {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
+ {0x1106, 0x0686, "VIA VT82C686", enable_flash_amd8111},
+ {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
+ {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100},
+ {0x1039, 0x0008, "SiS5595", enable_flash_sis5595},
+ {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536},
+ {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
+ {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
+ {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
+ {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
+ /* Slave, should not be here, to fix known bug for A01. */
+ {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804},
+ {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804},
+ {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804},
+ {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804},
+ {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804},
+ {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/
+ {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
+ {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
+ {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
+ {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
+ {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
+ {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
+ {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
+ {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
+ {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
};
+void print_supported_chipsets(void)
+{
+ int i;
+
+ printf("\nSupported chipsets:\n\n");
+
+ for (i = 0; i < ARRAY_SIZE(enables); i++)
+ printf("%s (%04x:%04x)\n", enables[i].name,
+ enables[i].vendor, enables[i].device);
+}
+
int chipset_flash_enable(void)
{
struct pci_dev *dev = 0;
@@ -524,8 +633,7 @@
int i;
/* Now let's try to find the chipset we have... */
- /* TODO: Use ARRAY_SIZE. */
- for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) {
+ for (i = 0; i < ARRAY_SIZE(enables); i++) {
dev = pci_dev_find(enables[i].vendor, enables[i].device);
if (dev)
break;
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/flashchips.c new/flashrom-svn-r3153/flashchips.c
--- old/flashrom-svn-r3061/flashchips.c 2008-01-19 01:04:46.000000000 +0100
+++ new/flashrom-svn-r3153/flashchips.c 2008-03-16 03:06:25.000000000 +0100
@@ -25,185 +25,116 @@
#include "msys_doc.h"
#endif
+/**
+ * List of supported flash ROM chips.
+ *
+ * Please keep the list sorted by vendor name and chip name, so that
+ * the output of 'flashrom -L' is alphabetically sorted.
+ */
struct flashchip flashchips[] = {
- {"Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024,
- probe_29f040b, erase_29f040b, write_29f040b},
- {"Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024,
- probe_29f040b, erase_29f040b, write_29f040b},
- {"Am29F016D", AMD_ID, AM_29F016D, 2048, 64 * 1024,
- probe_29f040b, erase_29f040b, write_29f040b},
- {"AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"At29C040A", ATMEL_ID, AT_29C040A, 512, 256,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"At29C020", ATMEL_ID, AT_29C020, 256, 256,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"At49F002(N)", ATMEL_ID, AT_49F002N, 256, 256,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"At49F002(N)T",ATMEL_ID, AT_49F002NT, 256, 256,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024,
- probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt},
- {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024,
- probe_29f002, erase_29f002, write_29f002},
- {"MX25L4005", MX_ID, MX_25L4005, 512, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"MX25L8005", MX_ID, MX_25L8005, 1024, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"SST25VF040B", SST_ID, SST_25VF040B, 512, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"SST28SF040A", SST_ID, SST_28SF040, 512, 256,
- probe_28sf040, erase_28sf040, write_28sf040},
- {"SST39SF010A", SST_ID, SST_39SF010, 128, 4096,
- probe_jedec, erase_chip_jedec, write_39sf020},
- {"SST39SF020A", SST_ID, SST_39SF020, 256, 4096,
- probe_jedec, erase_chip_jedec, write_39sf020},
- {"SST39SF040", SST_ID, SST_39SF040, 512, 4096,
- probe_jedec, erase_chip_jedec, write_39sf020},
- {"SST39VF020", SST_ID, SST_39VF020, 256, 4096,
- probe_jedec, erase_chip_jedec, write_39sf020},
-// assume similar to 004B, ignoring data sheet
- {"SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024,
- probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
-
- {"SST49LF040", SST_ID, SST_49LF040, 512, 4096,
- probe_jedec, erase_49lf040, write_49lf040},
- {"SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024,
- probe_jedec, erase_49lf040, write_49lf040},
- {"SST49LF080A", SST_ID, SST_49LF080A, 1024, 4096,
- probe_jedec, erase_49lf040, write_49lf040},
- {"SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024,
- probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
- {"SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024,
- probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
- {"SST49LF004A/B", SST_ID, SST_49LF004A, 512, 64 * 1024,
- probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
- {"SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024 ,
- probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
- {"SST49LF004C", SST_ID, SST_49LF004C, 512, 4 * 1024,
- probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc},
- {"SST49LF008C", SST_ID, SST_49LF008C, 1024, 4 * 1024 ,
- probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc},
- {"SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024 ,
- probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc},
- {"SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024 ,
- probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc},
- {"Pm49FL002", PMC_ID, PMC_49FL002, 256, 16 * 1024,
- probe_jedec, erase_chip_jedec, write_49fl004},
- {"Pm49FL004", PMC_ID, PMC_49FL004, 512, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_49fl004},
- {"W29C011", WINBOND_ID, W_29C011, 128, 128,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"W29C040P", WINBOND_ID, W_29C040P, 512, 256,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"W29C020C", WINBOND_ID, W_29C020C, 256, 128,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"W29EE011", WINBOND_ID, W_29C011, 128, 128,
- probe_w29ee011,erase_chip_jedec, write_jedec},
- {"W49F002U", WINBOND_ID, W_49F002U, 256, 128,
- probe_jedec, erase_chip_jedec, write_49f002},
- {"W49V002A", WINBOND_ID, W_49V002A, 256, 128,
- probe_jedec, erase_chip_jedec, write_49f002},
- {"W49V002FA", WINBOND_ID, W_49V002FA, 256, 128,
- probe_jedec, erase_chip_jedec, write_49f002},
- {"W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024,
- probe_jedec, erase_chip_jedec, write_39sf020},
- {"W39V040A", WINBOND_ID, W_39V040A, 512, 64*1024,
- probe_jedec, erase_chip_jedec, write_39sf020},
- {"W39V040B", WINBOND_ID, W_39V040B, 512, 64*1024,
- probe_jedec, erase_chip_jedec, write_39sf020},
- {"W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024,
- probe_jedec, erase_chip_jedec, write_39sf020},
- {"W25x10", WINBOND_NEX_ID, W_25X10, 128, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"W25x20", WINBOND_NEX_ID, W_25X20, 256, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"W25x40", WINBOND_NEX_ID, W_25X40, 512, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M29W040B", ST_ID, ST_M29W040B, 512, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M29F400BT", ST_ID, ST_M29F400BT, 512, 64 * 1024,
- probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt},
- {"M50FLW040A", ST_ID, ST_M50FLW040A, 512, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M29W010B", ST_ID, ST_M29W010B, 128, 16 * 1024,
- probe_jedec, erase_chip_jedec, write_jedec},
- {"M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024,
- probe_29f040b, erase_29f040b, write_29f040b},
- {"M25P05-A", ST_ID, ST_M25P05A, 64, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M25P10-A", ST_ID, ST_M25P10A, 128, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M25P20", ST_ID, ST_M25P20, 256, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M25P40", ST_ID, ST_M25P40, 512, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M25P80", ST_ID, ST_M25P80, 1024, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M25P16", ST_ID, ST_M25P16, 2048, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M25P32", ST_ID, ST_M25P32, 4096, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M25P64", ST_ID, ST_M25P64, 8192, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"M25P128", ST_ID, ST_M25P128, 16384, 256,
- probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
- {"82802ab", 137, 173, 512, 64 * 1024,
- probe_82802ab, erase_82802ab, write_82802ab},
- {"82802ac", 137, 172, 1024, 64 * 1024,
- probe_82802ab, erase_82802ab, write_82802ab},
- {"F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096,
- probe_jedec, erase_chip_jedec, write_49f002},
+ /******************************************************************************************************************************************************************************************************/
+ /* Vendor Chip Vendor ID Chip ID TODO TODO Probe function Erase function Write function Read function */
+ /******************************************************************************************************************************************************************************************************/
+ {"AMD", "Am29F016D", AMD_ID, AM_29F016D, 2048, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b},
+ {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b},
+ {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b},
+ {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, probe_jedec, erase_chip_jedec, write_jedec},
+ {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, probe_jedec, erase_chip_jedec, write_jedec},
+ {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, probe_jedec, erase_chip_jedec, write_jedec},
+ {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, probe_jedec, erase_chip_jedec, write_jedec},
+ {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, probe_jedec, erase_chip_jedec, write_jedec},
+ {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, probe_jedec, erase_chip_jedec, write_49f002},
+ {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, probe_jedec, erase_chip_jedec, write_jedec},
+ {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, probe_jedec, erase_chip_jedec, write_jedec},
+ {"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt},
+ {"Intel", "82802AB", INTEL_ID, 173, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab},
+ {"Intel", "82802AC", INTEL_ID, 172, 1024, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab},
+ {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"Macronix", "MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002},
#ifndef DISABLE_DOC
- {"MD-2802 (M-Systems DiskOnChip Millennium Module)",
- MSYSTEMS_ID, MSYSTEMS_MD2802,8, 8 * 1024,
- probe_md2802, erase_md2802, write_md2802, read_md2802},
+ {"M-Systems", "MD-2802", MSYSTEMS_ID, MSYSTEMS_MD2802, 8, 8 * 1024, probe_md2802, erase_md2802, write_md2802, read_md2802},
#endif
- {"LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024,
- probe_lhf00l04, erase_lhf00l04, write_lhf00l04},
- {"S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128,
- probe_jedec, erase_chip_jedec, write_49f002},
- {"S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128,
- probe_jedec, erase_chip_jedec, write_49f002},
- {"S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128,
- probe_jedec, erase_chip_jedec, write_49f002},
- {"S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128,
- probe_jedec, erase_chip_jedec, write_49f002},
- {"EON unknown SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID, 0, 0,
- probe_spi, NULL, NULL},
- {"MX unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0,
- probe_spi, NULL, NULL},
- {"SST unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0,
- probe_spi, NULL, NULL},
- {"ST unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0,
- probe_spi, NULL, NULL},
+ {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"PMC", "Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"PMC", "Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"PMC", "Pm49FL002", PMC_ID_NOPREFIX,PMC_49FL002, 256, 16 * 1024, probe_jedec, erase_chip_jedec, write_49fl004},
+ {"PMC", "Pm49FL004", PMC_ID_NOPREFIX,PMC_49FL004, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_49fl004},
+ {"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, probe_lhf00l04, erase_lhf00l04, write_lhf00l04},
+ {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, probe_28sf040, erase_28sf040, write_28sf040},
+ {"SST", "SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec},
+ {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, probe_jedec, erase_chip_jedec, write_39sf020},
+ {"SST", "SST39SF020A", SST_ID, SST_39SF020, 256, 4096, probe_jedec, erase_chip_jedec, write_39sf020},
+ {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, probe_jedec, erase_chip_jedec, write_39sf020},
+ {"SST", "SST39VF020", SST_ID, SST_39VF020, 256, 4096, probe_jedec, erase_chip_jedec, write_39sf020},
+// assume similar to 004B, ignoring data sheet
+ {"SST", "SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
+ {"SST", "SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
+ {"SST", "SST49LF004A/B", SST_ID, SST_49LF004A, 512, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
+ {"SST", "SST49LF004C", SST_ID, SST_49LF004C, 512, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc},
+ {"SST", "SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
+ {"SST", "SST49LF008C", SST_ID, SST_49LF008C, 1024, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc},
+ {"SST", "SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc},
+ {"SST", "SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, probe_jedec, erase_49lf040, write_49lf040},
+ {"SST", "SST49LF040", SST_ID, SST_49LF040, 512, 4096, probe_jedec, erase_49lf040, write_49lf040},
+ {"SST", "SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},
+ {"SST", "SST49LF080A", SST_ID, SST_49LF080A, 1024, 4096, probe_jedec, erase_49lf040, write_49lf040},
+ {"SST", "SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc},
+ {"ST", "M25P05-A", ST_ID, ST_M25P05A, 64, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M25P10-A", ST_ID, ST_M25P10A, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"ST", "M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b},
+ {"ST", "M29F400BT", ST_ID, ST_M29F400BT, 512, 64 * 1024, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt},
+ {"ST", "M29W010B", ST_ID, ST_M29W010B, 128, 16 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M29W040B", ST_ID, ST_M29W040B, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M50FLW040A", ST_ID, ST_M50FLW040A, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"ST", "M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab},
+ {"ST", "M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec},
+ {"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002},
+ {"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128, probe_jedec, erase_chip_jedec, write_49f002},
+ {"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, probe_jedec, erase_chip_jedec, write_49f002},
+ {"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002},
+ {"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read},
+ {"Winbond", "W29C011", WINBOND_ID, W_29C011, 128, 128, probe_jedec, erase_chip_jedec, write_jedec},
+ {"Winbond", "W29C020C", WINBOND_ID, W_29C020C, 256, 128, probe_jedec, erase_chip_jedec, write_jedec},
+ {"Winbond", "W29C040P", WINBOND_ID, W_29C040P, 512, 256, probe_jedec, erase_chip_jedec, write_jedec},
+ {"Winbond", "W29EE011", WINBOND_ID, W_29C011, 128, 128, probe_w29ee011, erase_chip_jedec, write_jedec},
+ {"Winbond", "W39V040A", WINBOND_ID, W_39V040A, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020},
+ {"Winbond", "W39V040B", WINBOND_ID, W_39V040B, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020},
+ {"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020},
+ {"Winbond", "W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020},
+ {"Winbond", "W49F002U", WINBOND_ID, W_49F002U, 256, 128, probe_jedec, erase_chip_jedec, write_49f002},
+ {"Winbond", "W49V002A", WINBOND_ID, W_49V002A, 256, 128, probe_jedec, erase_chip_jedec, write_49f002},
+ {"Winbond", "W49V002FA", WINBOND_ID, W_49V002FA, 256, 128, probe_jedec, erase_chip_jedec, write_49f002},
+
+ {"EON", "unknown SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL},
+ {"Macronix", "unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL},
+ {"PMC", "unknown SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL},
+ {"SST", "unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL},
+ {"ST", "unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL},
+
{NULL,}
};
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/flash.h new/flashrom-svn-r3153/flash.h
--- old/flashrom-svn-r3061/flash.h 2008-01-19 01:04:46.000000000 +0100
+++ new/flashrom-svn-r3153/flash.h 2008-03-15 00:55:58.000000000 +0100
@@ -30,7 +30,10 @@
#include
#include
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
struct flashchip {
+ const char *vendor;
const char *name;
/* With 32bit manufacture_id and model_id we can cover IDs up to
* (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
@@ -158,7 +161,20 @@
/* Programmable Micro Corp is listed in JEP106W in bank 2, so it should have
* a 0x7F continuation code prefix.
*/
-#define PMC_ID 0x9D /* PMC */
+#define PMC_ID 0x7F9D /* PMC */
+#define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */
+#define PMC_25LV512 0x7B
+#define PMC_25LV010 0x7C
+#define PMC_25LV020 0x7D
+#define PMC_25LV040 0x7E
+#define PMC_25LV080B 0x13
+#define PMC_25LV016B 0x14
+#define PMC_39LV512 0x1B
+#define PMC_39F010 0x1C /* also Pm39LV010 */
+#define PMC_39LV020 0x3D
+#define PMC_39LV040 0x3E
+#define PMC_39F020 0x4D
+#define PMC_39F040 0x4E
#define PMC_49FL002 0x6D
#define PMC_49FL004 0x6E
@@ -166,6 +182,14 @@
#define SHARP_LHF00L04 0xCF
/*
+ * Spansion was previously a joint venture of AMD and Fujitsu.
+ * S25 chips are SPI. The first device ID byte is memory type and
+ * the second device ID byte is memory capacity.
+ */
+#define SPANSION_ID 0x01 /* Spansion */
+#define SPANSION_S25FL016A 0x0214
+
+/*
* SST25 chips are SPI, first byte of device ID is memory type, second
* byte of device ID is related to log(bitsize) at least for some chips.
*/
@@ -266,11 +290,14 @@
struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
uint16_t card_vendor, uint16_t card_device);
+
/* board_enable.c */
int board_flash_enable(const char *vendor, const char *part);
+void print_supported_boards(void);
/* chipset_enable.c */
int chipset_flash_enable(void);
+void print_supported_chipsets(void);
/* Physical memory mapping device */
#if defined (__sun) && (defined(__i386) || defined(__amd64))
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/flashrom.8 new/flashrom-svn-r3153/flashrom.8
--- old/flashrom-svn-r3061/flashrom.8 2008-01-18 18:48:51.000000000 +0100
+++ new/flashrom-svn-r3153/flashrom.8 2008-03-12 12:54:51.000000000 +0100
@@ -2,13 +2,13 @@
.SH NAME
flashrom \- a universal BIOS/ROM/flash programming utility
.SH SYNOPSIS
-.B flashrom \fR[\fB\-rwvEVfh\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
+.B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
[\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
.SH DESCRIPTION
.B flashrom
is a universal flash programming utility for DIP, PLCC, or SPI flash ROM
chips. It can be used to flash BIOS/coreboot/firmware images, for example.
-
+.sp
(see
.B http://coreboot.org
for details on coreboot)
@@ -40,11 +40,11 @@
.B "\-e, \-\-eend" <addr>
Exclude end postion (obsolete).
.TP
-.B "\-m, \-\-mainboard" vendor:part
+.B "\-m, \-\-mainboard" <[vendor:]part>
Override mainboard settings. This option is needed for some mainboards,
see the
.B flashrom
-README for a list.
+README for a list. The vendor is not required when the board name is unique.
.TP
.B "\-f, \-\-force"
Force write without checking whether the ROM image file is really meant
@@ -61,11 +61,22 @@
.B <name>
from flash layout.
.TP
+.B "\-L, \-\-list\-supported"
+List the ROM chips, chipsets, and mainboards supported by flashrom.
+The list of mainboards consists of those boards which need a special
+ROM write-enable function for flashrom to work.
+.sp
+There are many other boards which will work out of the box, without such
+special support in flashrom. Some of the known-good/known-bad and tested ones
+are listed at
+.BR http://coreboot.org/Flashrom#Supported_mainboards ,
+but the list is not exhaustive, of course.
+.TP
.B "\-h, \-\-help"
Show a help text and exit.
-.\".TP
-.\".B "\-\-version"
-.\"Show version information and exit.
+.TP
+.B "\-R, \-\-version"
+Show version information and exit.
.SH BUGS
Please report any bugs at
.BR http://tracker.coreboot.org/trac/coreboot/newticket ","
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/flashrom.c new/flashrom-svn-r3153/flashrom.c
--- old/flashrom-svn-r3061/flashrom.c 2008-01-18 16:33:10.000000000 +0100
+++ new/flashrom-svn-r3153/flashrom.c 2008-03-16 00:41:19.000000000 +0100
@@ -129,9 +129,12 @@
*/
if (getpagesize() > size) {
+ /*
+ * if a flash size of 0 is mapped, we map a single page
+ * so we can probe in that area whether we know the
+ * vendor at least.
+ */
size = getpagesize();
- printf("WARNING: size: %d -> %ld (page size)\n",
- flash->total_size * 1024, (unsigned long)size);
}
bios = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
@@ -159,7 +162,11 @@
{
int idx;
int total_size = flash->total_size * 1024;
- volatile uint8_t *bios = flash->virtual_memory;
+ uint8_t *buf2 = (uint8_t *) calloc(total_size, sizeof(char));
+ if (flash->read == NULL)
+ memcpy(buf2, (const char *)flash->virtual_memory, total_size);
+ else
+ flash->read(flash, buf2);
printf("Verifying flash... ");
@@ -170,7 +177,7 @@
if (verbose && ((idx & 0xfff) == 0xfff))
printf("0x%08x", idx);
- if (*(bios + idx) != *(buf + idx)) {
+ if (*(buf2 + idx) != *(buf + idx)) {
if (verbose) {
printf("0x%08x ", idx);
}
@@ -189,28 +196,46 @@
return 0;
}
+void print_supported_chips(void)
+{
+ int i;
+
+ printf("Supported ROM chips:\n\n");
+
+ for (i = 0; flashchips[i].name != NULL; i++)
+ printf("%s %s\n", flashchips[i].vendor, flashchips[i].name);
+}
+
void usage(const char *name)
{
- printf("usage: %s [-rwvEVfh] [-c chipname] [-s exclude_start]\n", name);
- printf(" [-e exclude_end] [-m vendor:part] [-l file.layout] [-i imagename] [file]\n");
+ printf("usage: %s [-rwvEVfLhR] [-c chipname] [-s exclude_start]\n", name);
+ printf(" [-e exclude_end] [-m [vendor:]part] [-l file.layout] [-i imagename] [file]\n");
printf
- (" -r | --read: read flash and save into file\n"
- " -w | --write: write file into flash\n"
- " -v | --verify: verify flash against file\n"
- " -E | --erase: erase flash device\n"
- " -V | --verbose: more verbose output\n"
- " -c | --chip <chipname>: probe only for specified flash chip\n"
- " -s | --estart <addr>: exclude start position\n"
- " -e | --eend <addr>: exclude end postion\n"
- " -m | --mainboard vendor:part: override mainboard settings\n"
- " -f | --force: force write without checking image\n"
- " -l | --layout : read rom layout from file\n"
- " -i | --image <name>: only flash image name from flash layout\n"
- "\n" " If no file is specified, then all that happens"
+ (" -r | --read: read flash and save into file\n"
+ " -w | --write: write file into flash\n"
+ " -v | --verify: verify flash against file\n"
+ " -E | --erase: erase flash device\n"
+ " -V | --verbose: more verbose output\n"
+ " -c | --chip <chipname>: probe only for specified flash chip\n"
+ " -s | --estart <addr>: exclude start position\n"
+ " -e | --eend <addr>: exclude end postion\n"
+ " -m | --mainboard <[vendor:]part>: override mainboard settings\n"
+ " -f | --force: force write without checking image\n"
+ " -l | --layout : read rom layout from file\n"
+ " -i | --image <name>: only flash image name from flash layout\n"
+ " -L | --list-supported: print supported devices\n"
+ " -h | --help: print this help text\n"
+ " -R | --version: print the version (release)\n"
+ "\n" " If no file is specified, then all that happens"
" is that flash info is dumped.\n\n");
exit(1);
}
+void print_version(void)
+{
+ printf("flashrom r%s\n", FLASHROM_VERSION);
+}
+
int main(int argc, char *argv[])
{
uint8_t *buf;
@@ -235,7 +260,9 @@
{"force", 0, 0, 'f'},
{"layout", 1, 0, 'l'},
{"image", 1, 0, 'i'},
+ {"list-supported", 0, 0, 'L'},
{"help", 0, 0, 'h'},
+ {"version", 0, 0, 'R'},
{0, 0, 0, 0}
};
@@ -253,7 +280,7 @@
}
setbuf(stdout, NULL);
- while ((opt = getopt_long(argc, argv, "rwvVEfc:s:e:m:l:i:h",
+ while ((opt = getopt_long(argc, argv, "rRwvVEfc:s:e:m:l:i:Lh",
long_options, &option_index)) != EOF) {
switch (opt) {
case 'r':
@@ -290,8 +317,8 @@
lb_vendor = tempstr;
lb_part = tempstr2;
} else {
- printf("warning: ignored wrong format of"
- " mainboard: %s\n", tempstr);
+ lb_vendor = NULL;
+ lb_part = tempstr;
}
break;
case 'f':
@@ -306,6 +333,16 @@
tempstr = strdup(optarg);
find_romentry(tempstr);
break;
+ case 'L':
+ print_supported_chips();
+ print_supported_chipsets();
+ print_supported_boards();
+ exit(0);
+ break;
+ case 'R':
+ print_version();
+ exit(0);
+ break;
case 'h':
default:
usage(argv[0]);
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/layout.c new/flashrom-svn-r3153/layout.c
--- old/flashrom-svn-r3061/layout.c 2008-01-18 16:33:10.000000000 +0100
+++ new/flashrom-svn-r3153/layout.c 2008-03-04 17:29:54.000000000 +0100
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2005-2008 coresystems GmbH
+ * (Written by Stefan Reinauer for coresystems GmbH)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
#include
#include
#include
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/Makefile new/flashrom-svn-r3153/Makefile
--- old/flashrom-svn-r3061/Makefile 2008-01-18 17:17:44.000000000 +0100
+++ new/flashrom-svn-r3153/Makefile 2008-03-14 02:24:39.000000000 +0100
@@ -28,10 +28,18 @@
all: pciutils dep $(PROGRAM)
+# Set the flashrom version string from the highest revision number
+# of the checked out flashrom files.
+SVNDEF := -D'FLASHROM_VERSION="$(shell svnversion -cn . \
+ | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/")"'
+
$(PROGRAM): $(OBJS)
$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
$(STRIP) $(STRIP_ARGS) $(PROGRAM)
+flashrom.o: flashrom.c
+ $(CC) -c $(CFLAGS) $(SVNDEF) $(CPPFLAGS) $< -o $@
+
clean:
rm -f *.o *~
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/README new/flashrom-svn-r3153/README
--- old/flashrom-svn-r3061/README 2008-01-18 18:48:51.000000000 +0100
+++ new/flashrom-svn-r3153/README 2008-01-27 17:21:21.000000000 +0100
@@ -23,20 +23,20 @@
-----
$ flashrom [-rwvEVfh] [-c chipname] [-s exclude_start] [-e exclude_end]
- [-m vendor:part] [-l file.layout] [-i imagename] [file]
- -r | --read: read flash and save into file
- -w | --write: write file into flash (default when
- file is specified)
- -v | --verify: verify flash against file
- -E | --erase: erase flash device
- -V | --verbose: more verbose output
- -c | --chip <chipname>: probe only for specified flash chip
- -s | --estart <addr>: exclude start position
- -e | --eend <addr>: exclude end postion
- -m | --mainboard vendor:part: override mainboard settings
- -f | --force: force write without checking image
- -l | --layout : read rom layout from file
- -i | --image <name>: only flash image name from flash layout
+ [-m [vendor:]part] [-l file.layout] [-i imagename] [file]
+ -r | --read: read flash and save into file
+ -w | --write: write file into flash (default when
+ file is specified)
+ -v | --verify: verify flash against file
+ -E | --erase: erase flash device
+ -V | --verbose: more verbose output
+ -c | --chip <chipname>: probe only for specified flash chip
+ -s | --estart <addr>: exclude start position
+ -e | --eend <addr>: exclude end postion
+ -m | --mainboard <[vendor:]part>: override mainboard settings
+ -f | --force: force write without checking image
+ -l | --layout : read rom layout from file
+ -i | --image <name>: only flash image name from flash layout
If no file is specified, then all that happens
is that flash info is dumped and the flash chip is set to writable.
@@ -118,6 +118,7 @@
PMC PMC-49FL002
PMC PMC-49FL004
Sharp LHF-00L04
+Spansion S25FL016A
SST SST-29EE020A
SST SST-28SF040A
SST SST-39SF010A
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/rom.layout new/flashrom-svn-r3153/rom.layout
--- old/flashrom-svn-r3061/rom.layout 2005-11-26 22:55:36.000000000 +0100
+++ new/flashrom-svn-r3153/rom.layout 1970-01-01 01:00:00.000000000 +0100
@@ -1,3 +0,0 @@
-00000000:00008fff gfxrom
-00009000:0003ffff normal
-00040000:0007ffff fallback
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/spi.c new/flashrom-svn-r3153/spi.c
--- old/flashrom-svn-r3061/spi.c 2008-01-19 01:04:46.000000000 +0100
+++ new/flashrom-svn-r3153/spi.c 2008-02-06 23:07:58.000000000 +0100
@@ -94,7 +94,7 @@
uint16_t it8716f_flashport = 0;
/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
-int fast_spi=1;
+int fast_spi = 1;
void spi_prettyprint_status_register(struct flashchip *flash);
void spi_disable_blockprotect(void);
@@ -155,7 +155,7 @@
0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
printf("LPC write to serial flash %sabled\n",
(tmp & 1 << 4) ? "en" : "dis");
- printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
+ printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
/* LDN 0x7, reg 0x64/0x65 */
regwrite(port, 0x07, 0x7);
flashport = regval(port, 0x64) << 8;
@@ -227,12 +227,15 @@
* We can't use writecnt directly, but have to use a strange encoding.
*/
outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), port);
- do {
- busy = inb(port) & 0x80;
- } while (busy);
- for (i = 0; i < readcnt; i++) {
- readarr[i] = inb(port + 5 + i);
+ if (readcnt > 0) {
+ do {
+ busy = inb(port) & 0x80;
+ } while (busy);
+
+ for (i = 0; i < readcnt; i++) {
+ readarr[i] = inb(port + 5 + i);
+ }
}
return 0;
@@ -275,11 +278,17 @@
int probe_spi(struct flashchip *flash)
{
unsigned char readarr[3];
- uint8_t manuf_id;
- uint16_t model_id;
+ uint32_t manuf_id;
+ uint32_t model_id;
if (!generic_spi_rdid(readarr)) {
- manuf_id = readarr[0];
- model_id = (readarr[1] << 8) | readarr[2];
+ /* Check if this is a continuation vendor ID */
+ if (readarr[0] == 0x7f) {
+ manuf_id = (readarr[0] << 8) | readarr[1];
+ model_id = readarr[2];
+ } else {
+ manuf_id = readarr[0];
+ model_id = (readarr[1] << 8) | readarr[2];
+ }
printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id);
if (manuf_id == flash->manufacture_id &&
model_id == flash->model_id) {
@@ -345,14 +354,14 @@
*/
void spi_prettyprint_status_register_sst25vf016(uint8_t status)
{
- const char *bpt[]={
+ const char *bpt[] = {
"none",
"1F0000H-1FFFFFH",
"1E0000H-1FFFFFH",
"1C0000H-1FFFFFH",
"180000H-1FFFFFH",
"100000H-1FFFFFH",
- "all","all"
+ "all", "all"
};
printf_debug("Chip status register: Block Protect Write Disable "
"(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
@@ -446,7 +455,7 @@
generic_spi_write_enable();
outb(0x06 , it8716f_flashport + 1);
- outb(((2+(fast_spi?1:0)) << 4), it8716f_flashport);
+ outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
for (i = 0; i < 256; i++) {
bios[256 * block + i] = buf[256 * block + i];
}
@@ -510,18 +519,14 @@
{
int total_size = 1024 * flash->total_size;
int i;
- fast_spi=0;
+ fast_spi = 0;
spi_disable_blockprotect();
- for (i=0; i>16)&0xff,
- (address>>8)&0xff,
- (address>>0)&0xff,
+ (address >> 16) & 0xff,
+ (address >> 8) & 0xff,
+ (address >> 0) & 0xff,
};
/* Send Read */
@@ -548,13 +553,14 @@
{
int total_size = 1024 * flash->total_size;
int i;
- fast_spi=0;
+ fast_spi = 0;
if (total_size > 512 * 1024) {
- for (i = 0; i < total_size; i+=3) {
- int toread=3;
- if (total_size-i < toread) toread=total_size-i;
- spi_3byte_read(i, buf+i, toread);
+ for (i = 0; i < total_size; i += 3) {
+ int toread = 3;
+ if (total_size - i < toread)
+ toread = total_size - i;
+ spi_3byte_read(i, buf + i, toread);
}
} else {
memcpy(buf, (const char *)flash->virtual_memory, total_size);
diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/flashrom-svn-r3061/sst_fwhub.c new/flashrom-svn-r3153/sst_fwhub.c
--- old/flashrom-svn-r3061/sst_fwhub.c 2007-10-18 01:55:15.000000000 +0200
+++ new/flashrom-svn-r3153/sst_fwhub.c 2008-03-16 20:44:13.000000000 +0100
@@ -63,10 +63,19 @@
{
int i;
unsigned int total_size = flash->total_size * 1024;
+ volatile uint8_t *bios = flash->virtual_memory;
for (i = 0; i < total_size; i += flash->page_size)
erase_sst_fwhub_block(flash, i);
+ // dumb check if erase was successful.
+ for (i = 0; i < total_size; i++) {
+ if (bios[i] != 0xff) {
+ printf("ERASE FAILED!\n");
+ return -1;
+ }
+ }
+
return 0;
}
@@ -78,15 +87,8 @@
volatile uint8_t *bios = flash->virtual_memory;
// FIXME: We want block wide erase instead of ironing the whole chip
- erase_sst_fwhub(flash);
-
- // dumb check if erase was successful.
- for (i = 0; i < total_size; i++) {
- if (bios[i] != 0xff) {
- printf("ERASE FAILED!\n");
- return -1;
- }
- }
+ if (erase_sst_fwhub(flash))
+ return -1;
printf("Programming page: ");
for (i = 0; i < total_size / page_size; i++) {
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Remember to have fun...
---------------------------------------------------------------------
To unsubscribe, e-mail: opensuse-commit+unsubscribe@opensuse.org
For additional commands, e-mail: opensuse-commit+help@opensuse.org
