https://bugzilla.novell.com/show_bug.cgi?id=325917#c41
--- Comment #41 from Tejun Heo 2007-10-04 19:22:24 MST ---
10.2 uses IDE driver, piix, while 10.3 uses the libata one - ata_piix. The
chipset is ICH6 and it's almost impossible ata_piix driver has correctness
issue regarding BMDMA handling. It's just way too wildly used to have such
issue undiscovered till now.
All it does is pretty simple too. It sets up the memory descriptor table,
issues command to the drive and kicks DMA engine when it acks. There is no
fancy magic there and nothing much to fix for bad interaction with processor
power state.
This is getting confusing. I'll try to summarize ATA side of the story a bit.
* 10.2 uses IDE piix driver (not generic) and uses DMA mode happily.
* 10.3 uses libata ata_piix driver. And, no, different UDMA mode isn't related
to the cause of the problem at all. It starts at the same transfer rate as in
10.2 but slows down in an attempt to resolve repeated timeouts.
* Thomas was right in that this isn't a IRQ delivery problem. BMDMA and TF
status indicate that data transfer isn't complete when timeout occurs. DMA
engine got stuck for some reason.
* No, I don't think ata_piix and/or libata in general have BMDMA handling bugs.
It's too hot a path to have such issue.
Here are my understanding of the processor side of the story.
* SL102 and 103 uses the same mechanism to put the CPU into powersave mode
(ACPI Cx)
* Disabling C3 and C4 fixes the problem.
And I have a question. Is it possible that SL102 didn't put the processor into
C3 or C4 while ATA DMA was in progress, for whatever reason including plain
dumb luck (ie. timer was too frequent or whatever)?
I think we need to instrument switching into/back from C3 and whether ARB_DIS,
BM_STS and BM_RLD are working and being handled properly. Broken handling of
those bits seem like the most likely cause to me. ATA controllers and drivers
just don't play much, if any, role in all those cache coherency management and
bus arbitration blocking.
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