On Thu, 4 Jan 2018 17:47:28 +0100 (CET) Yamaban <foerster@lisas.de> wrote:
Well, no. "The Issue" dated back to the development of the "Pentium Pro", the 32bit dual-core Pentium from 1995.
Intel found out the hard way that the branch prediction engine they planned to include was a mass grave of transistors, thus immensely expensive and drove the already low yield of the production down to single digits of percents. So, to get even a kind of a grip at the situation, the whole branch prediction engine was re-designed. Much simpler, used less cycles, used not even a tenth of the transistors. Intel hyped that as "Productivity Enhanced" Branch Prediction in the pre-release days.
The documentation of the Pentium Pro clearly stated the restrictions the reduced branch prediction unit had, and the compilers at the time handled that with the needed care.
Fast forward to around 2005, the race between Intel and AMD got "not nice" and thus Intel "optimised" its own compiler to reduce the prior as "must have" declared security checks to gain speed. In the name of performance over everything else this kind of optimisation found its way into other code. Databases, OS-kernels, compilers. You can easily do the math. Using a non paranoid compiler opens you up the the holes now published (they where found before October 2017). (Much of the harshness of the situation is the dramatically risen level of visualisation compared to ten years ago.)
I am not a world-class expert in this, but I was watching and writing about this tech at the time. I have not heard about the details you're talking about here. Note, please, I am not saying you're wrong! There was a significant step that you don't mention though. The Pentium Pro was the first Intel micro-architecture (called P6) to break down instructions into micro-operations and do out-of-order execution on them (AFAICR.) The Pentium Pro was the basis of the Pentium II and Pentium III, with essentially the same P6 architecture. The Pentium 4 was a new chip with a new architecture, Netburst. Notably, along with everything else, it had an all-new branch-prediction unit. It was famous for high clock speeds, low instructions-per-clock (IPC) rate, running very hot and generally not being a great CPU family. AMD's Sledgehammer architecture (Athlon 64/Opteron) thrashed it. So, Intel Israel got the job of designing a successor. They produced the Pentium M low-power-draw chip for laptops: a P6 core, but on the new bus of the Pentium 4 and with Netburst's improved branch prediction unit. It had good IPC, ran cool, and was a success. Around the same time, Intel India was working on quad-core P4 CPUs. Due to violating Intel's strict policies on nepotism and cronyism, Intel India was shut down, meaning the end of the planned future line of Netburst CPUs. Intel switched emphasis to the Pentium M. Intel Texas got the job of updating the P4 line with dual-core models (2 separate CPU dies in 1 package) and with adapting AMD's 64-bit instruction set extensions. (Intel had devised its own x86-64 extension but Microsoft vetoed it. MS said it was already supporting x86-32, Itanium and AMD64, and would not additionally support another 64-bit instruction set architecture. Intel scrapped its own x86-64 ISA and implemented AMD's instead.) Meanwhile, Intel Israel enhanced the Pentium M to produce the 32-bit Core processors, and then those were enhanced to support AMD64, creating the Core 2 series. Netburst was discontinued, in a huge, humiliating and very expensive climb-down and turnaround for Intel. AFAICT, the Core series was where what's now being called Meltdown began. I.e. with the incorporation of the Netburst branch-prediction unit into a descendant of the P6 microarchitecture. -- Liam Proven - Technical Writer, SUSE Linux s.r.o. Corso II, Křižíkova 148/34, 186-00 Praha 8 - Karlín, Czechia Email: lproven@suse.com - Office telephone: +420 284 241 084 -- To unsubscribe, e-mail: opensuse+unsubscribe@opensuse.org To contact the owner, e-mail: opensuse+owner@opensuse.org