On 2016-02-13 23:29, Greg Freemyer wrote:
On Sat, Feb 13, 2016 at 5:10 PM, Carlos E. R.
Actually, I don't know how this is handled.
That's one reason multi-tier cache is so valuable. Each core has it's own dedicated cache as I understand it so there are a lot of memory accesses that never go out to the DIMMs.
Yes, but it also needs dedicated main RAM.
As to ram itself, DDR4 (or at least some implementations of DDR4) have quad memory channels so 4 different cores can be pulling data simultaneously.
I don't know when this becomes really useful, but I suspect the 6-core PC I recently built isn't really taking advantage of all 4 quad channels.
IIRC, my board and memory has 3 memory channels. But we are talking now of big machines with dozens of cores or chips. With only a few channels, there will be collisions. When I was studying, the books said that they did not know yet how to handle this situation. -- Cheers / Saludos, Carlos E. R. (from 13.1 x86_64 "Bottle" at Telcontar)