More powermanagement stuff to try out

Matthias Hopf

5 Jun 2009 5 Jun '09

16:54

After some discussion with AMD we found that there is a chance that with only some additional AtomBIOS calls we might be able to get to the same power levels as fglrx. With the following patch these are included, but only called if Option "ForceLowPowerMode" is active. I'd like to have this tested before I actually commit this. I tested it here and it *seems* to work - I don't have a power meter at hand for validation at the moment. What we're still missing are - PCIe lane changes - Memory clock changes - Dynamic clock changes - Core voltage changes For all of them enough documentation is available already. So if *this* patch actually helps reducing power consumption, we probably have enough information for fully implemented power management. What we're still missing information for are - Which clock/voltage settings are stable - What is the minimum core / memory clock Maybe we'll find something by looking at the V4 version of the PowerPlay AtomBIOS table (of which we currently don't know the details yet). Maybe it helps smoking something while staring at the hexdumps =->>> CU & happy weekend Matthias -- Matthias Hopf __ __ __ Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__ mat@mshopf.de Phone +49-911-74053-715 __) |_| __) |__ R & D www.mshopf.de

Attachments:

0001-Add-AtomBIOS-based-static-powermanagement-enablement.patch (text/x-patch — 4.7 KB)

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Matthias Hopf

8 Jun 8 Jun

11:49

On Jun 05, 09 18:54:44 +0200, Matthias Hopf wrote:

...

With the following patch these are included, but only called if Option "ForceLowPowerMode" is active. I'd like to have this tested before I actually commit this. I tested it here and it *seems* to work - I don't have a power meter at hand for validation at the moment.

It's committed to master now. Matthias -- Matthias Hopf __ __ __ Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__ mat@mshopf.de Phone +49-911-74053-715 __) |_| __) |__ R & D www.mshopf.de -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Rafał Miłecki

9 Jun 9 Jun

11:57

2009/6/5 Matthias Hopf :

...

After some discussion with AMD we found that there is a chance that with only some additional AtomBIOS calls we might be able to get to the same power levels as fglrx.

With the following patch these are included, but only called if Option "ForceLowPowerMode" is active. I'd like to have this tested before I actually commit this. I tested it here and it *seems* to work - I don't have a power meter at hand for validation at the moment.

What we're still missing are - PCIe lane changes - Memory clock changes - Dynamic clock changes - Core voltage changes

For all of them enough documentation is available already. So if *this* patch actually helps reducing power consumption, we probably have enough information for fully implemented power management.

What we're still missing information for are - Which clock/voltage settings are stable - What is the minimum core / memory clock

Maybe we'll find something by looking at the V4 version of the PowerPlay AtomBIOS table (of which we currently don't know the details yet). Maybe it helps smoking something while staring at the hexdumps =->>>

I've some newbie questions. First of all, why do we use DynamicClockGating only for (rhdPtr->ChipSet < RHD_R600)? Is this enabled by default on everything newer than R600? How does DynamicClockGating work? Does GPU knows itself all (unused) hardware blocks than he can stop clocking? What actually is EnableASIC_StaticPwrMgt? Is this something we need to enable before using DynamicClockGating? If so, what other AtomBIOS commands depend on EnableASIC_StaticPwrMgt? Could someone explain shortly other AtomBIOS commands like: ASIC_StaticPwrMgtStatusChange, DynamicMemorySettings, MemoryTraining -- Rafał Miłecki -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Matthias Hopf

12:47

On Jun 09, 09 13:57:45 +0200, Rafał Miłecki wrote:

...

First of all, why do we use DynamicClockGating only for (rhdPtr->ChipSet < RHD_R600)? Is this enabled by default on everything newer than R600?

Apparently we just don't know what this is doing on R6xx and up. If you want to experiment here, be my guest! I'd love to change this to something more reasonable for R6xx as well, but we need more and especially consistent tests including measuring used power for that.

...

How does DynamicClockGating work? Does GPU knows itself all (unused) hardware blocks than he can stop clocking?

Good question. No idea.

...

What actually is EnableASIC_StaticPwrMgt? Is this something we need to enable before using DynamicClockGating? If so, what other AtomBIOS commands depend on EnableASIC_StaticPwrMgt?

Good question. Again, no idea. This code is basically ported from radeon. Alex implemented it there, I assume by asking bios guys what to do to reduce power consumption.

...

Could someone explain shortly other AtomBIOS commands like: ASIC_StaticPwrMgtStatusChange, DynamicMemorySettings, MemoryTraining

Memory training is necessary for DDR5 memory only. And AFAIK it's done automatically. Matthias -- Matthias Hopf __ __ __ Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__ mat@mshopf.de Phone +49-911-74053-715 __) |_| __) |__ R & D www.mshopf.de -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Alex Deucher

14:56

2009/6/9 Rafał Miłecki :

...

2009/6/5 Matthias Hopf :

...
After some discussion with AMD we found that there is a chance that with only some additional AtomBIOS calls we might be able to get to the same power levels as fglrx.

With the following patch these are included, but only called if Option "ForceLowPowerMode" is active. I'd like to have this tested before I actually commit this. I tested it here and it *seems* to work - I don't have a power meter at hand for validation at the moment.

What we're still missing are - PCIe lane changes - Memory clock changes - Dynamic clock changes - Core voltage changes

For all of them enough documentation is available already. So if *this* patch actually helps reducing power consumption, we probably have enough information for fully implemented power management.

What we're still missing information for are - Which clock/voltage settings are stable - What is the minimum core / memory clock

Maybe we'll find something by looking at the V4 version of the PowerPlay AtomBIOS table (of which we currently don't know the details yet). Maybe it helps smoking something while staring at the hexdumps =->>>

I've some newbie questions.

First of all, why do we use DynamicClockGating only for (rhdPtr->ChipSet < RHD_R600)? Is this enabled by default on everything newer than R600?

This table is empty on r6xx hardware. The hw is different on r6xx and newer asics.

...

How does DynamicClockGating work? Does GPU knows itself all (unused) hardware blocks than he can stop clocking?

The GPU will turn off the clock to various blocks on the chip when they are idle to save power. When they are requested, they are powered back up. You can pick at the block level which blocks participate or not.

...

What actually is EnableASIC_StaticPwrMgt? Is this something we need to enable before using DynamicClockGating? If so, what other AtomBIOS commands depend on EnableASIC_StaticPwrMgt?

It enables automatic lower clocks for things like PCI D states. I'm not sure it makes much difference under normal circumstances.

...

Could someone explain shortly other AtomBIOS commands like: ASIC_StaticPwrMgtStatusChange, DynamicMemorySettings, MemoryTraining

I'm not sure what the former is used for. I suspect it's used when changing power states. The latter two are used for memory setup and are called by other tables like SetMemoryClock or AsicInit. Alex -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Rafał Miłecki

15:08

W dniu 9 czerwca 2009 16:56 użytkownik Alex Deucher napisał:

...

2009/6/9 Rafał Miłecki :

...
First of all, why do we use DynamicClockGating only for (rhdPtr->ChipSet < RHD_R600)? Is this enabled by default on everything newer than R600?

This table is empty on r6xx hardware. The hw is different on r6xx and newer asics.

Ah, I missed that. Indeed, it's empty on my M82. Still, how does clock gating look on hw >= R600? Can I enable it somehow? Using registers only? Or maybe it is enabled by default? -- Rafał Miłecki -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Alex Deucher

15:31

2009/6/9 Rafał Miłecki :

...

W dniu 9 czerwca 2009 16:56 użytkownik Alex Deucher napisał:

...
2009/6/9 Rafał Miłecki :

...
First of all, why do we use DynamicClockGating only for (rhdPtr->ChipSet < RHD_R600)? Is this enabled by default on everything newer than R600?

This table is empty on r6xx hardware. The hw is different on r6xx and newer asics.

Ah, I missed that. Indeed, it's empty on my M82.

Still, how does clock gating look on hw >= R600? Can I enable it somehow? Using registers only? Or maybe it is enabled by default?

It's completely different and I haven't been able to find out exactly how it works yet. Alex -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Matthias Hopf

25 Jun 25 Jun

10:47

On Jun 05, 09 18:54:44 +0200, Matthias Hopf wrote:

...

After some discussion with AMD we found that there is a chance that with only some additional AtomBIOS calls we might be able to get to the same power levels as fglrx.

With the following patch these are included, but only called if Option "ForceLowPowerMode" is active. I'd like to have this tested before

Unfortunately, these have no additional effect. Moreover, with the newer cards (GDDR5 memory) the most power saving comes from lowering the memory clock - something that probably cannot be done during runtime without display glitches, and also something that didn't prove stable enough yet according to Rafal's tests (because we don't wait correctly for engine idle AFAIR).

...

What we're still missing are - PCIe lane changes - Memory clock changes - Dynamic clock changes - Core voltage changes

This is still missing. Matthias -- Matthias Hopf __ __ __ Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__ mat@mshopf.de Phone +49-911-74053-715 __) |_| __) |__ R & D www.mshopf.de -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Dariem Pérez Herrera

26 Jun 26 Jun

05:46

New subject: RS600 still not working

Hi, Some time ago, I wrote about issues with GPU RS600. Now, with new updates (linux-2.6.30, latest mesa, xorg and radeonhd from git repos) the same problems persist. "MC not idle" is the tipical error message in log. My card (Radeon Xpress 1250) works fine with "radeon" driver (although with no acceleration and no SVIDEO output detection). I've been trying to hack a little into the source code of radeonhd and I found incorrect values for certain registers addresses for RS600. I'm attaching a patch. Before this changes, my notebook totally froze when starting X, leaving me with the only option to shut it down through power button. Now I just get a black screen, but the keyboard keeps responsive, so now I can restart it properly. That happened before, because the function to detect idle MC couldn't detect it, because of the incorrectly set registers, and now it works fine, telling me the error at the proper time, but still.... I also attached my Xorg.0.log with -logverbose 7. I can see there are many functions been called which names suggest they are made for RS690, not RS600, so it is possible that MC cannot go idle because of this (incorrectly use of RS690 register addresses instead RS600 addresses). I'm not familiar with radeonhd source code, so trying to fix MC make me lost into the code ocean. Any mentorship or documentation available so I can try? best regards, Dariem (II) config/hal: initialized X.Org X Server 1.5.3 Release Date: 5 November 2008 X Protocol Version 11, Revision 0 Build Operating System: Linux 2.6.30 i686 Current Operating System: Linux dariem-pc 2.6.30 #1 SMP PREEMPT Fri Jun 12 02:28:12 CDT 2009 i686 Build Date: 21 June 2009 02:31:46PM Before reporting problems, check http://wiki.x.org to make sure that you have the latest version. Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/Xorg.0.log", Time: Fri Jun 26 00:37:30 2009 (==) Using config file: "/etc/X11/xorg.conf" (==) No Layout section. Using the first Screen section. (==) No screen section available. Using defaults. (**) |-->Screen "Default Screen Section" (0) (**) | |-->Monitor "<default monitor>" (==) No device specified for screen "Default Screen Section". Using the first device section listed. (**) | |-->Device "Card0" (==) No monitor specified for screen "Default Screen Section". Using a default monitor configuration. (==) Automatically adding devices (==) Automatically enabling devices (==) FontPath set to: /usr/share/fonts/misc/, /usr/share/fonts/TTF/, /usr/share/fonts/OTF, /usr/share/fonts/Type1/, /usr/share/fonts/100dpi/, /usr/share/fonts/75dpi/, built-ins (==) ModulePath set to "/usr/lib/xorg/modules" (II) Cannot locate a core pointer device. (II) Cannot locate a core keyboard device. (II) The server relies on HAL to provide the list of input devices. If no devices become available, reconfigure HAL or disable AllowEmptyInput. (II) Open ACPI successful (/var/run/acpid.socket) (II) Loader magic: 0xeb0 (II) Module ABI versions: X.Org ANSI C Emulation: 0.4 X.Org Video Driver: 4.1 X.Org XInput driver : 2.1 X.Org Server Extension : 1.1 (II) Loader running on linux (--) using VT number 7 (--) PCI:*(0@1:5:0) ATI Technologies Inc Radeon Xpress 1250 rev 0, Mem @ 0xd8000000/0, 0xd0100000/0, I/O @ 0x00009000/0 (II) System resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [4] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [5] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) LoadModule: "extmod" (II) Loading /usr/lib/xorg/modules/extensions//libextmod.so (II) Module extmod: vendor="X.Org Foundation" compiled for 1.5.3, module version = 1.0.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 1.1 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "dbe" (II) Loading /usr/lib/xorg/modules/extensions//libdbe.so (II) Module dbe: vendor="X.Org Foundation" compiled for 1.5.3, module version = 1.0.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 1.1 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "glx" (II) Loading /usr/lib/xorg/modules/extensions//libglx.so (II) Module glx: vendor="X.Org Foundation" compiled for 1.5.3, module version = 1.0.0 ABI class: X.Org Server Extension, version 1.1 (==) AIGLX enabled (==) Exporting typical set of GLX visuals (II) Loading extension GLX (II) LoadModule: "record" (II) Loading /usr/lib/xorg/modules/extensions//librecord.so (II) Module record: vendor="X.Org Foundation" compiled for 1.5.3, module version = 1.13.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 1.1 (II) Loading extension RECORD (II) LoadModule: "dri" (II) Loading /usr/lib/xorg/modules/extensions//libdri.so (II) Module dri: vendor="X.Org Foundation" compiled for 1.5.3, module version = 1.0.0 ABI class: X.Org Server Extension, version 1.1 (II) Loading extension XFree86-DRI (II) LoadModule: "radeonhd" (II) Loading /usr/lib/xorg/modules/drivers//radeonhd_drv.so (II) Module radeonhd: vendor="AMD GPG" compiled for 1.5.3, module version = 1.2.5 Module class: X.Org Video Driver ABI class: X.Org Video Driver, version 4.1 (II) RADEONHD: X driver for the following AMD GPG (ATI) graphics devices: RV505 : Radeon X1550, X1550 64bit. RV515 : Radeon X1300, X1550, X1600; FireGL V3300, V3350. RV516 : Radeon X1300, X1550, X1550 64-bit, X1600; FireMV 2250. R520 : Radeon X1800; FireGL V5300, V7200, V7300, V7350. RV530 : Radeon X1300 XT, X1600, X1600 Pro, X1650; FireGL V3400, V5200. RV535 : Radeon X1300, X1650. RV550 : Radeon X2300 HD. RV560 : Radeon X1650. RV570 : Radeon X1950, X1950 GT; FireGL V7400. R580 : Radeon X1900, X1950; AMD Stream Processor. R600 : Radeon HD 2900 GT/Pro/XT; FireGL V7600/V8600/V8650. RV610 : Radeon HD 2350, HD 2400 Pro/XT, HD 2400 Pro AGP; FireGL V4000. RV620 : Radeon HD 3450, HD 3470. RV630 : Radeon HD 2600 LE/Pro/XT, HD 2600 Pro/XT AGP; Gemini RV630; FireGL V3600/V5600. RV635 : Radeon HD 3650, HD 3670. RV670 : Radeon HD 3690, 3850, HD 3870, FireGL V7700, FireStream 9170. R680 : Radeon HD 3870 X2. M52 : Mobility Radeon X1300. M54 : Mobility Radeon X1400; M54-GL. M56 : Mobility Radeon X1600; Mobility FireGL V5200. M58 : Mobility Radeon X1800, X1800 XT; Mobility FireGL V7100, V7200. M62 : Mobility Radeon X1350. M64 : Mobility Radeon X1450, X2300. M66 : Mobility Radeon X1700, X1700 XT; FireGL V5250. M68 : Mobility Radeon X1900. M71 : Mobility Radeon HD 2300. M72 : Mobility Radeon HD 2400; Radeon E2400. M74 : Mobility Radeon HD 2400 XT. M76 : Mobility Radeon HD 2600; (Gemini ATI) Mobility Radeon HD 2600 XT. M82 : Mobility Radeon HD 3400. M86 : Mobility Radeon HD 3650, HD 3670, Mobility FireGL V5700. M88 : Mobility Radeon HD 3850, HD 3850 X2, HD 3870, HD3870 X2. RS600 : Radeon Xpress 1200, Xpress 1250. RS690 : Radeon X1200, X1250, X1270. RS740 : RS740, RS740M. RS780 : Radeon HD 3100/3200/3300 Series. R700 : Radeon R700. RV710 : Radeon HD4570, HD4350. RV730 : Radeon HD4670, HD4650. RV740 : Radeon HD4770. EXPERIMENTAL AND UNTESTED. RV770 : Radeon HD 4800 Series; Everest, K2, Denali ATI FirePro. RV790 : Radeon HD 4890. M92 : Mobility Radeon HD4330, HD4530, HD4570. EXPERIMENTAL. M93 : Mobility Radeon M93. EXPERIMENTAL AND UNTESTED. M96 : Mobility Radeon HD4600. M97 : Mobility Radeon HD4860. EXPERIMENTAL AND UNTESTED. M98 : Mobility Radeon HD4850, HD4870. (II) RADEONHD: version 1.2.5, built from git branch master, commit fbc7fbfa + changes (II) Primary Device is: PCI 01@00:05:0 (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [4] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [5] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) resource ranges after probing: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [4] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [5] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [6] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [7] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [8] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [9] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [10] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) RADEONHD(0): Creating default Display subsection in Screen section "Default Screen Section" for depth/fbbpp 24/32 (==) RADEONHD(0): Depth 24, (--) framebuffer bpp 32 (**) RADEONHD(0): Option "AccelMethod" "EXA" (**) RADEONHD(0): Option "DRI" "false" (**) RADEONHD(0): Selected EXA 2D acceleration. (II) RADEONHD(0): Unknown card detected: 0x7942:0x144D:0xC036. If - and only if - your card does not work or does not work optimally please contact radeonhd@opensuse.org to help rectify this. Use the subject: 0x7942:0x144D:0xC036: <name of board> and *please* describe the problems you are seeing in your message. (--) RADEONHD(0): Detected an RS600 on an unidentified card (II) RADEONHD(0): FUNCTION: rhdMapMMIO (II) RADEONHD(0): Mapped IO @ 0xd0100000 to 0xb7b47000 (size 0x00010000) (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomInit (II) RADEONHD(0): Getting BIOS copy from legacy VBIOS location (II) RADEONHD(0): FUNCTION: rhdAtomGetTables (II) RADEONHD(0): ATOM BIOS Rom: SubsystemVendorID: 0x144d SubsystemID: 0xc036 IOBaseAddress: 0x9000 Filename: Br22542F.bin BIOS Bootup Message: ATI Radeon Xpress 1250 for Samsung/Firenze2 (II) RADEONHD(0): Call to AtomBIOS Init succeeded (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomAnalogTVInfoQuery (II) RADEONHD(0): Analog TV Default Mode: 1 (II) RADEONHD(0): Found default TV Mode NTSC (II) RADEONHD(0): FUNCTION: rhdGetVideoRamSize (--) RADEONHD(0): VideoRAM: 131072 kByte (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomVramInfoQuery (II) RADEONHD(0): Framebuffer space used by Firmware (kb): 20 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomVramInfoQuery (II) RADEONHD(0): Start of VRAM area used by Firmware: 0x7ffb000 (II) RADEONHD(0): AtomBIOS requests 20kB of VRAM scratch space (II) RADEONHD(0): AtomBIOS VRAM scratch base: 0x7ffb000 (II) RADEONHD(0): Call to AtomBIOS Set FB Space succeeded (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Default Engine Clock: 500000 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Default Memory Clock: 333000 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Output: 1200000 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Minimum Pixel ClockPLL Frequency Output: 0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Input: 13500 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Minimum Pixel ClockPLL Frequency Input: 1000 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Maximum Pixel Clock: 400000 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Reference Clock: 14320 (II) RADEONHD(0): FUNCTION: RHDDRIPreInit (II) RADEONHD(0): Direct rendering explicitly turned off. (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Module "i2c" already built-in (II) RADEONHD(0): FUNCTION: RHDI2CFunc (II) RADEONHD(0): FUNCTION: rhdGetI2CPrescale (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Default Engine Clock: 500000 (II) RADEONHD(0): FUNCTION: rhdInitI2C (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Clk_Mask: 0x1f90 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Clk_Mask_Shift: 0x0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Data_Mask: 0x1f90 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Data_Mask_Shift: 0x8 (II) RADEONHD(0): I2C clock prescale value: 7f27 (II) RADEONHD(0): I2C bus "RHD I2C line 0" initialized. (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Clk_Mask: 0x1f90 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Clk_Mask_Shift: 0x0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Data_Mask: 0x1f94 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Data_Mask_Shift: 0x8 (II) RADEONHD(0): I2C clock prescale value: 7f27 (II) RADEONHD(0): I2C bus "RHD I2C line 1" initialized. (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Clk_Mask: 0x1f90 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Clk_Mask_Shift: 0x0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Data_Mask: 0x1f98 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Data_Mask_Shift: 0x8 (II) RADEONHD(0): I2C clock prescale value: 7f27 (II) RADEONHD(0): I2C bus "RHD I2C line 2" initialized. (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Clk_Mask: 0x1f90 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Clk_Mask_Shift: 0x0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Data_Mask: 0x1f98 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGPIOI2CInfoQuery (II) RADEONHD(0): GPIO_I2C_Data_Mask_Shift: 0x8 (II) RADEONHD(0): I2C clock prescale value: 7f27 (II) RADEONHD(0): I2C bus "RHD I2C line 3" initialized. (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Module "ddc" already built-in (II) RADEONHD(0): FUNCTION: RHDVGAInit (II) RADEONHD(0): Detected VGA mode. (II) RADEONHD(0): FUNCTION: RHDMCInit (II) RADEONHD(0): MC FB Address: 0x00000000. (II) RADEONHD(0): FUNCTION: RHDCrtcsInit (II) RADEONHD(0): FUNCTION: rhdInitScaleType (II) RADEONHD(0): FUNCTION: RHDPLLsInit (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Minimum Pixel ClockPLL Frequency Output: 0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Output: 1200000 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Maximum Pixel Clock: 400000 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomFirmwareInfoQuery (II) RADEONHD(0): Reference Clock: 14320 (II) RADEONHD(0): FUNCTION: RHDAudioInit (II) RADEONHD(0): FUNCTION: RHDLUTsInit (II) RADEONHD(0): FUNCTION: RHDCursorsInit (II) RADEONHD(0): FB: Allocated Cursor Image at offset 0x00000000 (size = 0x00004000) (II) RADEONHD(0): FB: Allocated Cursor Image at offset 0x00004000 (size = 0x00004000) (II) RADEONHD(0): FUNCTION: RHDPmInit (II) RADEONHD(0): FUNCTION: RHDConnectorsInit (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomConnectorInfo (II) RADEONHD(0): FUNCTION: rhdAtomConnectorInfoFromObjectHeader (II) RADEONHD(0): FUNCTION: rhdAtomConnectorInfoFromSupportedDevices (II) RADEONHD(0): AtomBIOS Connector[0]: VGA Device: CRT1 Output: 1 (II) RADEONHD(0): FUNCTION: rhdAtomGetDDCIndex (II) RADEONHD(0): Found DDC GPIO Index: 0 HW DDC 0 NO HPD (II) RADEONHD(0): AtomBIOS Connector[1]: PANEL Device: LCD1 Output: 4 (II) RADEONHD(0): FUNCTION: rhdAtomGetDDCIndex (II) RADEONHD(0): Found DDC GPIO Index: 1 HW DDC 1 NO HPD (II) RADEONHD(0): AtomBIOS Connector[2]: SVIDEO Device: TV1 Output: 1 NO DDC NO HPD (II) RADEONHD(0): Connector[0] {RHD_CONNECTOR_VGA, "VGA CRT1", RHD_DDC_0, RHD_HPD_NONE, { RHD_OUTPUT_DACA, RHD_OUTPUT_NONE } } (II) RADEONHD(0): Connector[1] {RHD_CONNECTOR_PANEL, "PANEL LCD1", RHD_DDC_1, RHD_HPD_NONE, { RHD_OUTPUT_LVTMA, RHD_OUTPUT_NONE } } (II) RADEONHD(0): Connector[2] {RHD_CONNECTOR_TV, "SVIDEO TV1", RHD_DDC_NONE, RHD_HPD_NONE, { RHD_OUTPUT_DACA, RHD_OUTPUT_NONE } } (II) RADEONHD(0): Call to AtomBIOS Get Connectors succeeded (II) RADEONHD(0): FUNCTION: RHDHPDSave (II) RADEONHD(0): FUNCTION: RHDHPDSet (II) RADEONHD(0): RHDConnectorsInit: 0 (VGA CRT1) type 1, ddc 0, hpd 0 (II) RADEONHD(0): FUNCTION: RHDI2CFunc (II) RADEONHD(0): FUNCTION: RHDDACAInit (II) RADEONHD(0): FUNCTION: RHDOutputAdd (--) RADEONHD(0): Attaching Output DAC A to Connector VGA 1 (II) RADEONHD(0): RHDConnectorsInit: 1 (PANEL LCD1) type 4, ddc 1, hpd 0 (II) RADEONHD(0): FUNCTION: RHDI2CFunc (II) RADEONHD(0): FUNCTION: RHDLVTMAInit (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS SEQ Dig onto DE: 30 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS SEQ DE to BL: 360 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS Off Delay: 500 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS Duallink: 0x0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS 24Bit: 0x0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS FPDI: 0x0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS Temporal Dither : 0x1 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS Spatial Dither : 0x0 (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsInfoQuery (II) RADEONHD(0): LVDS Grey Level: 0x3 (II) RADEONHD(0): AtomBIOS returned 3 Grey Levels (--) RADEONHD(0): Detected a 18bit single link panel. (II) RADEONHD(0): Printing LVDS paramaters: MacroControl: 0x08A11703 TXClockPattern: 0x0063 PowerDigToDE: 0x001E PowerDEToBL: 0x0168 OffDelay: 0x01F4 PowerRefDiv: 0x0848 BlonRefDiv: 0x00C7 (II) RADEONHD(0): LVDSDebugBacklight: PWRSEQ BLON State: on (II) RADEONHD(0): LVDSDebugBacklight: BLON: off BLON_OVRD: disabled BLON_POL: non-invert (II) RADEONHD(0): LVDSDebugBacklight: BL_MOD: enable BL_MOD_LEVEL: 255 BL_MOD_RES: 255 (II) RADEONHD(0): FUNCTION: RHDOutputAdd (--) RADEONHD(0): Attaching Output LVDS to Connector PANEL (II) RADEONHD(0): RHDConnectorsInit: 2 (SVIDEO TV1) type 5, ddc 255, hpd 0 (--) RADEONHD(0): Attaching Output DAC A to Connector TV SVIDEO (II) RADEONHD(0): FUNCTION: RHDHPDRestore (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomOutputDeviceList (II) RADEONHD(0): FUNCTION: rhdAtomOutputDeviceListFromObjectHeader (II) RADEONHD(0): FUNCTION: rhdAtomOutputDeviceListFromSupportedDevices (II) RADEONHD(0): Call to AtomBIOS Get Output Info succeeded (II) RADEONHD(0): FUNCTION: RHDAtomSetupOutputDriverPrivate (II) RADEONHD(0): FUNCTION: RHDAtomSetupOutputDriverPrivate (II) RADEONHD(0): FUNCTION: RHDRandrPreInit (II) RADEONHD(0): RandR: Adding RRoutput VGA_1 for Output DAC A (II) RADEONHD(0): RandR: Adding RRoutput PANEL for Output LVDS (II) RADEONHD(0): RandR: Adding RRoutput TV_SVIDEO for Output DAC A (II) RADEONHD(0): Output VGA_1 has no monitor section (II) RADEONHD(0): Output VGA_1 has no monitor section (II) RADEONHD(0): Output PANEL has no monitor section (II) RADEONHD(0): Output TV_SVIDEO has no monitor section (II) RADEONHD(0): rhdRROutputDetect: Output VGA_1 (II) RADEONHD(0): FUNCTION: DACASense (II) RADEONHD(0): DACSense: DAC: 0x00 (II) RADEONHD(0): rhdRROutputDetect: Output PANEL (II) RADEONHD(0): rhdRROutputGetModes: Output PANEL (II) RADEONHD(0): FUNCTION: RHDMonitorInit (II) RADEONHD(0): FUNCTION: rhdMonitorPanel (II) RADEONHD(0): I2C device "RHD I2C line 1:ddc2" registered at address 0xA0. (II) RADEONHD(0): FUNCTION: rhdRS69WriteRead (II) RADEONHD(0): FUNCTION: rhdRS69I2CSetupStatus (II) RADEONHD(0): FUNCTION: rhdRS69I2CStatus (II) RADEONHD(0): FUNCTION: rhdRS69WriteRead (II) RADEONHD(0): FUNCTION: rhdRS69I2CSetupStatus (II) RADEONHD(0): FUNCTION: rhdRS69I2CStatus (II) RADEONHD(0): FUNCTION: rhdRS69WriteRead (II) RADEONHD(0): FUNCTION: rhdRS69I2CSetupStatus (II) RADEONHD(0): FUNCTION: rhdRS69I2CStatus (II) RADEONHD(0): FUNCTION: rhdRS69WriteRead (II) RADEONHD(0): FUNCTION: rhdRS69I2CSetupStatus (II) RADEONHD(0): FUNCTION: rhdRS69I2CStatus (II) RADEONHD(0): I2C device "RHD I2C line 1:ddc2" removed. (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsGetTimings (II) RADEONHD(0): FUNCTION: rhdAtomLvdsTimings (II) RADEONHD(0): rhdAtomLvdsTimings: LVDS Modeline: 1280x800 68900 1280 (1280) 1301 1333 (1408) 1408 800 (800) 804 808 (816) 816 (II) RADEONHD(0): Call to AtomBIOS Get Panel Mode succeeded (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomLvdsGetTimings (II) RADEONHD(0): Query for AtomBIOS Get Panel EDID: failed (II) RADEONHD(0): FUNCTION: RHDRRMonitorInit (II) RADEONHD(0): FUNCTION: RHDSynthModes (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "320x200Scaled" 5.75 320 368 400 480 200 203 209 215 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "320x240Scaled" 7.00 320 368 400 480 240 243 247 253 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "640x480Scaled" 23.75 640 688 720 800 480 483 487 494 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "720x480Scaled" 26.25 720 768 800 880 480 483 493 499 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "854x480Scaled" 30.25 854 902 934 1014 480 483 493 499 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "768x576Scaled" 33.25 768 816 848 928 576 579 583 593 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "800x600Scaled" 35.75 800 848 880 960 600 603 607 618 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1024x768Scaled" 56.50 1024 1072 1104 1184 768 771 775 790 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1152x768Scaled" 62.50 1152 1200 1232 1312 768 771 781 790 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1280x720Scaled" 64.50 1280 1328 1360 1440 720 723 728 741 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1280x960Scaled" 86.00 1280 1328 1360 1440 960 963 967 988 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1280x854Scaled" 76.50 1280 1328 1360 1440 854 857 867 879 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1280x960Scaled" 86.00 1280 1328 1360 1440 960 963 967 988 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1280x1024Scaled" 91.75 1280 1328 1360 1440 1024 1027 1034 1054 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1440x960Scaled" 95.50 1440 1488 1520 1600 960 963 973 988 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1400x1050Scaled" 101.75 1400 1448 1480 1560 1050 1053 1057 1081 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1680x1050Scaled" 120.00 1680 1728 1760 1840 1050 1053 1059 1081 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1600x1200Scaled" 131.25 1600 1648 1680 1760 1200 1203 1207 1235 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1920x1080Scaled" 139.75 1920 1968 2000 2080 1080 1083 1088 1111 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "1920x1200Scaled" 155.25 1920 1968 2000 2080 1200 1203 1209 1235 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "2048x1536Scaled" 211.00 2048 2096 2128 2208 1536 1539 1543 1580 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "2560x1600Scaled" 270.75 2560 2608 2640 2720 1600 1603 1609 1646 +hsync -vsync (II) RADEONHD(0): RHDSynthModes: Adding Modeline Modeline "2560x2048Scaled" 346.50 2560 2608 2640 2720 2048 2051 2058 2107 +hsync -vsync (II) RADEONHD(0): Found native mode: Modeline "1280x800" 68.90 1280 1301 1333 1408 800 804 808 816 (II) RADEONHD(0): FUNCTION: RHDRRValidateScaledToMode (II) RADEONHD(0): FUNCTION: LVDSModeValid (WW) RADEONHD(0): No monitor size info, assuming 96dpi. (II) RADEONHD(0): rhdRROutputGetModes: Adding Output Modes: Modeline "1280x800" 68.90 1280 1301 1333 1408 800 804 808 816 Modeline "320x200Scaled" 5.75 320 368 400 480 200 203 209 215 +hsync -vsync Modeline "320x240Scaled" 7.00 320 368 400 480 240 243 247 253 +hsync -vsync Modeline "640x480Scaled" 23.75 640 688 720 800 480 483 487 494 +hsync -vsync Modeline "720x480Scaled" 26.25 720 768 800 880 480 483 493 499 +hsync -vsync Modeline "854x480Scaled" 30.25 854 902 934 1014 480 483 493 499 +hsync -vsync Modeline "768x576Scaled" 33.25 768 816 848 928 576 579 583 593 +hsync -vsync Modeline "800x600Scaled" 35.75 800 848 880 960 600 603 607 618 +hsync -vsync Modeline "1024x768Scaled" 56.50 1024 1072 1104 1184 768 771 775 790 +hsync -vsync Modeline "1152x768Scaled" 62.50 1152 1200 1232 1312 768 771 781 790 +hsync -vsync Modeline "1280x720Scaled" 64.50 1280 1328 1360 1440 720 723 728 741 +hsync -vsync Modeline "1280x960Scaled" 86.00 1280 1328 1360 1440 960 963 967 988 +hsync -vsync Modeline "1280x854Scaled" 76.50 1280 1328 1360 1440 854 857 867 879 +hsync -vsync Modeline "1280x960Scaled" 86.00 1280 1328 1360 1440 960 963 967 988 +hsync -vsync Modeline "1280x1024Scaled" 91.75 1280 1328 1360 1440 1024 1027 1034 1054 +hsync -vsync Modeline "1440x960Scaled" 95.50 1440 1488 1520 1600 960 963 973 988 +hsync -vsync Modeline "1400x1050Scaled" 101.75 1400 1448 1480 1560 1050 1053 1057 1081 +hsync -vsync Modeline "1680x1050Scaled" 120.00 1680 1728 1760 1840 1050 1053 1059 1081 +hsync -vsync Modeline "1600x1200Scaled" 131.25 1600 1648 1680 1760 1200 1203 1207 1235 +hsync -vsync Modeline "1920x1080Scaled" 139.75 1920 1968 2000 2080 1080 1083 1088 1111 +hsync -vsync Modeline "1920x1200Scaled" 155.25 1920 1968 2000 2080 1200 1203 1209 1235 +hsync -vsync Modeline "2048x1536Scaled" 211.00 2048 2096 2128 2208 1536 1539 1543 1580 +hsync -vsync Modeline "2560x1600Scaled" 270.75 2560 2608 2640 2720 1600 1603 1609 1646 +hsync -vsync Modeline "2560x2048Scaled" 346.50 2560 2608 2640 2720 2048 2051 2058 2107 +hsync -vsync (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1280x800 Modeline "1280x800" 68.90 1280 1301 1333 1408 800 804 808 816 (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1280x800: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 320x200Scaled Modeline "320x200Scaled" 5.75 320 368 400 480 200 203 209 215 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 320x200Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 320x240Scaled Modeline "320x240Scaled" 7.00 320 368 400 480 240 243 247 253 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 320x240Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 640x480Scaled Modeline "640x480Scaled" 23.75 640 688 720 800 480 483 487 494 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 640x480Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 720x480Scaled Modeline "720x480Scaled" 26.25 720 768 800 880 480 483 493 499 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 720x480Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 854x480Scaled Modeline "854x480Scaled" 30.25 854 902 934 1014 480 483 493 499 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 854x480Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 768x576Scaled Modeline "768x576Scaled" 33.25 768 816 848 928 576 579 583 593 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 768x576Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 800x600Scaled Modeline "800x600Scaled" 35.75 800 848 880 960 600 603 607 618 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 800x600Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1024x768Scaled Modeline "1024x768Scaled" 56.50 1024 1072 1104 1184 768 771 775 790 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1024x768Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1152x768Scaled Modeline "1152x768Scaled" 62.50 1152 1200 1232 1312 768 771 781 790 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1152x768Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1280x720Scaled Modeline "1280x720Scaled" 64.50 1280 1328 1360 1440 720 723 728 741 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1280x720Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1280x960Scaled Modeline "1280x960Scaled" 86.00 1280 1328 1360 1440 960 963 967 988 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1280x960Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1280x854Scaled Modeline "1280x854Scaled" 76.50 1280 1328 1360 1440 854 857 867 879 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1280x854Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1280x960Scaled Modeline "1280x960Scaled" 86.00 1280 1328 1360 1440 960 963 967 988 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1280x960Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1280x1024Scaled Modeline "1280x1024Scaled" 91.75 1280 1328 1360 1440 1024 1027 1034 1054 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1280x1024Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1440x960Scaled Modeline "1440x960Scaled" 95.50 1440 1488 1520 1600 960 963 973 988 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1440x960Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1400x1050Scaled Modeline "1400x1050Scaled" 101.75 1400 1448 1480 1560 1050 1053 1057 1081 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1400x1050Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1680x1050Scaled Modeline "1680x1050Scaled" 120.00 1680 1728 1760 1840 1050 1053 1059 1081 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1680x1050Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1600x1200Scaled Modeline "1600x1200Scaled" 131.25 1600 1648 1680 1760 1200 1203 1207 1235 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1600x1200Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1920x1080Scaled Modeline "1920x1080Scaled" 139.75 1920 1968 2000 2080 1080 1083 1088 1111 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1920x1080Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1920x1200Scaled Modeline "1920x1200Scaled" 155.25 1920 1968 2000 2080 1200 1203 1209 1235 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1920x1200Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 2048x1536Scaled Modeline "2048x1536Scaled" 211.00 2048 2096 2128 2208 1536 1539 1543 1580 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 2048x1536Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 2560x1600Scaled Modeline "2560x1600Scaled" 270.75 2560 2608 2640 2720 1600 1603 1609 1646 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 2560x1600Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 2560x2048Scaled Modeline "2560x2048Scaled" 346.50 2560 2608 2640 2720 2048 2051 2058 2107 +hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 2560x2048Scaled: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 640x480 Modeline "640x480" 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 640x480: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 320x240 Modeline "320x240" 12.59 320 328 376 400 240 245 246 262 doublescan -hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 320x240: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 800x600 Modeline "800x600" 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 800x600: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 400x300 Modeline "400x300" 18.00 400 412 448 512 300 300 301 312 doublescan +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 400x300: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 800x600 Modeline "800x600" 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 800x600: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 400x300 Modeline "400x300" 20.00 400 420 484 528 300 300 302 314 doublescan +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 400x300: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1024x768 Modeline "1024x768" 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1024x768: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 512x384 Modeline "512x384" 32.50 512 524 592 672 384 385 388 403 doublescan -hsync -vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 512x384: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1280x960 Modeline "1280x960" 108.00 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1280x960: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 640x480 Modeline "640x480" 54.00 640 688 744 900 480 480 482 500 doublescan +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 640x480: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1280x1024 Modeline "1280x1024" 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1280x1024: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 640x512 Modeline "640x512" 54.00 640 664 720 844 512 512 514 533 doublescan +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 640x512: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1600x1200 Modeline "1600x1200" 162.00 1600 1664 1856 2160 1200 1201 1204 1250 +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1600x1200: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 800x600 Modeline "800x600" 81.00 800 832 928 1080 600 600 602 625 doublescan +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 800x600: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1792x1344 Modeline "1792x1344" 204.80 1792 1920 2120 2448 1344 1345 1348 1394 -hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1792x1344: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 896x672 Modeline "896x672" 102.40 896 960 1060 1224 672 672 674 697 doublescan -hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 896x672: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1856x1392 Modeline "1856x1392" 218.30 1856 1952 2176 2528 1392 1393 1396 1439 -hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1856x1392: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 928x696 Modeline "928x696" 109.15 928 976 1088 1264 696 696 698 719 doublescan -hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 928x696: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1920x1440 Modeline "1920x1440" 234.00 1920 2048 2256 2600 1440 1441 1444 1500 -hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1920x1440: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 960x720 Modeline "960x720" 117.00 960 1024 1128 1300 720 720 722 750 doublescan -hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 960x720: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1400x1050 Modeline "1400x1050" 122.00 1400 1488 1640 1880 1050 1052 1064 1082 +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1400x1050: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 700x525 Modeline "700x525" 61.00 700 744 820 940 525 526 532 541 doublescan +hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 700x525: doublescan mode not supported (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 2048x1536 Modeline "2048x1536" 266.95 2048 2200 2424 2800 1536 1537 1540 1589 -hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 2048x1536: Mode OK (II) RADEONHD(0): FUNCTION: rhdRROutputModeValid (II) RADEONHD(0): rhdRROutputModeValid: Output PANEL : 1024x768 Modeline "1024x768" 133.47 1024 1100 1212 1400 768 768 770 794 doublescan -hsync +vsync (II) RADEONHD(0): FUNCTION: RHDRRModeFixup (II) RADEONHD(0): rhdRROutputModeValid: 1024x768: doublescan mode not supported (II) RADEONHD(0): rhdRROutputDetect: Output TV_SVIDEO (II) RADEONHD(0): Output VGA_1 disconnected (II) RADEONHD(0): Output PANEL connected (II) RADEONHD(0): Output TV_SVIDEO disconnected (II) RADEONHD(0): Using exact sizes for initial modes (II) RADEONHD(0): Output PANEL using initial mode 1280x800 (II) RADEONHD(0): RandR 1.2 support enabled (==) RADEONHD(0): RGB weight 888 (==) RADEONHD(0): Default visual is TrueColor (==) RADEONHD(0): Using gamma correction (1.0, 1.0, 1.0) (II) RADEONHD(0): FUNCTION: RHDGetVirtualFromConfig (II) RADEONHD(0): FUNCTION: DxFBValid: CRTC 1 (II) RADEONHD(0): FUNCTION: DxFBValid: CRTC 2 (II) RADEONHD(0): Using 2560x2560 Framebuffer with 2560 pitch (II) RADEONHD(0): FB: Allocated ScanoutBuffer at offset 0x00008000 (size = 0x01900000) (==) RADEONHD(0): DPI set to (96, 96) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/lib/xorg/modules//libfb.so (II) Module fb: vendor="X.Org Foundation" compiled for 1.5.3, module version = 1.0.0 ABI class: X.Org ANSI C Emulation, version 0.4 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Module "ramdac" already built-in (II) Loading sub module "exa" (II) LoadModule: "exa" (II) Loading /usr/lib/xorg/modules//libexa.so (II) Module exa: vendor="X.Org Foundation" compiled for 1.5.3, module version = 2.4.0 ABI class: X.Org Video Driver, version 4.1 (II) RADEONHD(0): FB: Allocated Offscreen Buffer at offset 0x01908000 (size = 0x00CCB000) (II) RADEONHD(0): Free FB offset 0x025D3000 (size = 0x05A2D000) (II) RADEONHD(0): FUNCTION: rhdUnmapMMIO (--) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [4] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [5] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [6] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [7] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [8] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [9] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [10] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) RADEONHD(0): FUNCTION: RHDScreenInit (II) RADEONHD(0): FUNCTION: rhdMapMMIO (II) RADEONHD(0): Mapped IO @ 0xd0100000 to 0xb7b47000 (size 0x00010000) (II) RADEONHD(0): FUNCTION: rhdMapFB (II) RADEONHD(0): Physical FB Address: 0xD8000000 (PCI BAR: 0xD8000000) (II) RADEONHD(0): Mapped FB @ 0xd8000000 to 0xafa88000 (size 0x08000000) (II) RADEONHD(0): FUNCTION: rhdSave (II) RADEONHD(0): FUNCTION: RHDMCSave (II) RADEONHD(0): FUNCTION: RHDVGASave (II) RADEONHD(0): FUNCTION: rhdVGASaveFB (II) RADEONHD(0): FUNCTION: RHDMCGetFBLocation (WW) RADEONHD(0): rhdVGASaveFB: Unable to access the VGA framebuffer (0x38000000) (II) RADEONHD(0): FUNCTION: RHDOutputsSave (II) RADEONHD(0): FUNCTION: DACASave (II) RADEONHD(0): FUNCTION: LVDSSave (II) RADEONHD(0): FUNCTION: RHDSaveBiosScratchRegisters (II) RADEONHD(0): FUNCTION: RHDPLLsSave (II) RADEONHD(0): FUNCTION: R500PLL1Save (II) RADEONHD(0): FUNCTION: R500PLL2Save (II) RADEONHD(0): FUNCTION: RHDAudioSave (II) RADEONHD(0): FUNCTION: RHDLUTsSave (II) RADEONHD(0): FUNCTION: LUTxSave (II) RADEONHD(0): FUNCTION: LUTxSave (II) RADEONHD(0): RHDCrtcSave: CRTC 1 (II) RADEONHD(0): Saved CrtcCountControl[0] = 0x00000000 (II) RADEONHD(0): RHDCrtcSave: CRTC 2 (II) RADEONHD(0): Saved CrtcCountControl[1] = 0x00000000 (II) RADEONHD(0): FUNCTION: rhdSaveCursor (II) RADEONHD(0): FUNCTION: saveCursor (II) RADEONHD(0): FUNCTION: saveCursor (II) RADEONHD(0): FUNCTION: RHDPmSave (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomGetClock (II) RADEONHD(0): FUNCTION: RHDAtomBiosFunc (II) RADEONHD(0): FUNCTION: rhdAtomExec (II) RADEONHD(0): FUNCTION: atomSaveRegisters (II) RADEONHD(0): ParseTable said: CD_SUCCESS (II) RADEONHD(0): Call to AtomBIOS Exec succeeded (II) RADEONHD(0): Current Engine Clock: 501200 (II) RADEONHD(0): FUNCTION: RHDVGADisable (II) RADEONHD(0): FUNCTION: D1Power (II) RADEONHD(0): D1CRTCDisable: 0 loops (II) RADEONHD(0): FUNCTION: D2Power (II) RADEONHD(0): FUNCTION: RHDMCIdleWait (II) RADEONHD(0): RHDMCIdleWait: MC not idle (EE) RADEONHD(0): MC not idle Fatal server error: AddScreen/ScreenInit failed for driver 0

Matthias Hopf

10:30

New subject: RS600 still not working

On Jun 26, 09 01:46:41 -0400, Dariem Pérez Herrera wrote:

...

Some time ago, I wrote about issues with GPU RS600. Now, with new updates (linux-2.6.30, latest mesa, xorg and radeonhd from git repos) the same problems persist. "MC not idle" is the tipical error message in log. My card (Radeon Xpress 1250) works fine with "radeon" driver (although with no acceleration and no SVIDEO output detection). I've been trying to hack a little into the source code of radeonhd and I found incorrect values for certain registers addresses for RS600. I'm attaching a patch. Before this

Note that radeon typically uses the MMIO register space, while radeonhd is programming the MC over the PCIe register space. If you don't take care of that, chances are that you're just *disabling* MC programming - that was something that made RS740 sort-of fly as well. Note that - in addition to different register spaces - MC registers are always programmed indirect. That is, you write the meta-register-number into one register (address), and the value in a different (data). For reading you write the meta-register-number into the address register, and read out the data register. I had the plan to rework this to use MMIO as well, but haven't come around to so far. If you take that into account, and can make RS600 work by just exchanging the values in the RS690 case, I can make that work for the general case.

...

I also attached my Xorg.0.log with -logverbose 7. I can see there are many functions been called which names suggest they are made for RS690, not RS600, so it is possible that MC cannot go idle because of this (incorrectly use of RS690 register addresses instead RS600 addresses). I'm

It's more probably, that we don't know how to correctly check the RS600's MC for being idle :-]

...

not familiar with radeonhd source code, so trying to fix MC make me lost into the code ocean. Any mentorship or documentation available so I can try?

Sorry, there's just the code. And the MC code is one of the scariest places, even with the abstraction level we have in radeonhd. CU Matthias -- Matthias Hopf __ __ __ Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__ mat@mshopf.de Phone +49-911-74053-715 __) |_| __) |__ R & D www.mshopf.de -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Dariem Pérez Herrera

17:56

New subject: RS600 still not working

Matthias Hopf escribió:

...

On Jun 26, 09 01:46:41 -0400, Dariem Pérez Herrera wrote: Note that radeon typically uses the MMIO register space, while radeonhd is programming the MC over the PCIe register space. If you don't take care of that, chances are that you're just *disabling* MC programming - that was something that made RS740 sort-of fly as well.

Interesting... but then... why function RHDMCIdleWait() didn't stopped execution when idling MC failed (before I changed the registers) and instead some later assertion stopped the execution because of the same problem (MC was not idle), and then, when I changed the registers addresses, now RHDMCIdleWait() correctly reports "MC is not idle" before the later assertion which I think should never had been triggered??

...

Note that - in addition to different register spaces - MC registers are always programmed indirect. That is, you write the meta-register-number into one register (address), and the value in a different (data). For reading you write the meta-register-number into the address register, and read out the data register.

hmmm....I see...

...

If you take that into account, and can make RS600 work by just exchanging the values in the RS690 case, I can make that work for the general case.

The problem is as you explained before, radeonhd use a different register space than radeon, so if that is the case, I don't have any documentation or information about the addresses used by RS600 over PCIe register space, and I can't use radeon driver as example which uses MMIO.... am I correct? So, what can I do?

...

It's more probably, that we don't know how to correctly check the RS600's MC for being idle :-]

...
not familiar with radeonhd source code, so trying to fix MC make me lost into the code ocean. Any mentorship or documentation available so I can try?

Sorry, there's just the code. And the MC code is one of the scariest places, even with the abstraction level we have in radeonhd.

I would like to help, but without any documentation or specification, what can I do? BTW, how do you get the specification for coding this driver? best regards, Dariem -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Matthias Hopf

30 Jun 30 Jun

13:09

New subject: RS600 still not working

On Jun 26, 09 13:56:22 -0400, Dariem Pérez Herrera wrote:

...

Interesting... but then... why function RHDMCIdleWait() didn't stopped execution when idling MC failed (before I changed the registers) and instead some later assertion stopped the execution because of the same problem (MC was not idle), and then, when I changed the registers addresses, now RHDMCIdleWait() correctly reports "MC is not idle" before the later assertion which I think should never had been triggered??

Because when you changed the register addresses, you disabled MC programming, which stay in their original setting. Thus are idle (somewhat). But this may introduce other issues (which, I don't know).

...

The problem is as you explained before, radeonhd use a different register space than radeon, so if that is the case, I don't have any documentation or information about the addresses used by RS600 over PCIe register space, and I can't use radeon driver as example which uses MMIO.... am I correct? So, what can I do?

I actually wanted to re-program the MC setup to use the same registers as radeon in the MMIO space, but never got around to that. If you want to experiment a little, please try to do that, and check whether that works for you.

...

...
Sorry, there's just the code. And the MC code is one of the scariest places, even with the abstraction level we have in radeonhd.

I would like to help, but without any documentation or specification, what can I do? BTW, how do you get the specification for coding this driver?

They are basically at http://www.x.org/docs/AMD/ as described on the wiki. We have received a little bit of additional information from AMD, but that is not opened up yet :-( Also, all this information has to be taken with a grain of salt, the open source guys have a difficult time at extracting the relevant (and even more difficult: correct) information from the engineers. Matthias -- Matthias Hopf __ __ __ Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__ mat@mshopf.de Phone +49-911-74053-715 __) |_| __) |__ R & D www.mshopf.de -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Alex Deucher

28 Jun 28 Jun

18:37

New subject: RS600 still not working

2009/6/26 Dariem Pérez Herrera :

...

Hi, Some time ago, I wrote about issues with GPU RS600. Now, with new updates (linux-2.6.30, latest mesa, xorg and radeonhd from git repos) the same problems persist. "MC not idle" is the tipical error message in log. My card (Radeon Xpress 1250) works fine with "radeon" driver (although with no acceleration and no SVIDEO output detection). I've been trying to hack a little into the source code of radeonhd and I found incorrect values for certain registers addresses for RS600. I'm attaching a patch. Before this changes, my notebook totally froze when starting X, leaving me with the only option to shut it down through power button. Now I just get a black screen, but the keyboard keeps responsive, so now I can restart it properly. That happened before, because the function to detect idle MC couldn't detect it, because of the incorrectly set registers, and now it works fine, telling me the error at the proper time, but still.... I also attached my Xorg.0.log with -logverbose 7. I can see there are many functions been called which names suggest they are made for RS690, not RS600, so it is possible that MC cannot go idle because of this (incorrectly use of RS690 register addresses instead RS600 addresses). I'm not familiar with radeonhd source code, so trying to fix MC make me lost into the code ocean. Any mentorship or documentation available so I can try?

The radeon driver should have the correct bits for indirect MC access on RS690/740 and RS600. Note that RS690/740 and RS600 are different WRT MC setup. See: RADEONINMC() RADEONOUTMC() radeon_get_mc_idle() in radeon_driver.c for the relevant regs and bits. Alex -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Dariem Pérez Herrera

29 Jun 29 Jun

06:39

New subject: RS600 still not working

Alex Deucher escribió:

...

2009/6/26 Dariem Pérez Herrera :

...
(...) I also attached my Xorg.0.log with -logverbose 7. I can see there are many functions been called which names suggest they are made for RS690, not RS600, so it is possible that MC cannot go idle because of this (incorrectly use of RS690 register addresses instead RS600 addresses). I'm not familiar with radeonhd source code, so trying to fix MC make me lost into the code ocean. Any mentorship or documentation available so I can try?

The radeon driver should have the correct bits for indirect MC access on RS690/740 and RS600. Note that RS690/740 and RS600 are different WRT MC setup. See: RADEONINMC() RADEONOUTMC() radeon_get_mc_idle() in radeon_driver.c for the relevant regs and bits.

Alex

Thanks for the tip, I'm seeing the code right now. I'll try to do my best on bringing RS600 full support to radeonhd. best regards, Dariem -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Dariem Pérez Herrera

10:04

New subject: RS600 still not working

Alex Deucher escribió:

...

2009/6/26 Dariem Pérez Herrera :

...
I also attached my Xorg.0.log with -logverbose 7. I can see there are many functions been called which names suggest they are made for RS690, not RS600, so it is possible that MC cannot go idle because of this (incorrectly use of RS690 register addresses instead RS600 addresses). I'm not familiar with radeonhd source code, so trying to fix MC make me lost into the code ocean. Any mentorship or documentation available so I can try?

The radeon driver should have the correct bits for indirect MC access on RS690/740 and RS600. Note that RS690/740 and RS600 are different WRT MC setup. See: RADEONINMC() RADEONOUTMC() radeon_get_mc_idle() in radeon_driver.c for the relevant regs and bits.

Alex

Alex, What about the difference between MMIO register space used by radeon driver, and PCIe register space used by radeonhd? Is there any way to convert from the first to the second and vice-versa? Is it relevant at all? best regards, Dariem -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Dariem Pérez Herrera

10:17

New subject: RS600 still not working

Dariem Pérez Herrera escribió:

...

Alex Deucher escribió:

...
The radeon driver should have the correct bits for indirect MC access on RS690/740 and RS600. Note that RS690/740 and RS600 are different WRT MC setup. See: RADEONINMC() RADEONOUTMC() radeon_get_mc_idle() in radeon_driver.c for the relevant regs and bits.

Alex

Alex, What about the difference between MMIO register space used by radeon driver, and PCIe register space used by radeonhd? Is there any way to convert from the first to the second and vice-versa? Is it relevant at all?

best regards,

Dariem

Forget the previous message, now I'm seeing radeonhd source code and I can see _RHDWriteMC() uses RHDRegWrite() to write MC for RS600, which is an alias for MMIO_OUT32() with some level of indirection ;-) . Thanks anyway. Dariem -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

David C. Rankin

21:10

New subject: RS600 still not working

On Monday 29 June 2009 05:17:37 am Dariem Pérez Herrera wrote:

...

Dariem Pérez Herrera escribió:

...
Alex Deucher escribió:

...
The radeon driver should have the correct bits for indirect MC access on RS690/740 and RS600. Note that RS690/740 and RS600 are different WRT MC setup. See: RADEONINMC() RADEONOUTMC() radeon_get_mc_idle() in radeon_driver.c for the relevant regs and bits.

Alex

Alex, What about the difference between MMIO register space used by radeon driver, and PCIe register space used by radeonhd? Is there any way to convert from the first to the second and vice-versa? Is it relevant at all?

best regards,

Dariem

Forget the previous message, now I'm seeing radeonhd source code and I can see _RHDWriteMC() uses RHDRegWrite() to write MC for RS600, which is an alias for MMIO_OUT32() with some level of indirection ;-) . Thanks anyway.

Dariem

Dariem, I'm not a programmer, but I have a laptop with the RS690M and I'm happy to test patches, etc. if you need help there. -- David C. Rankin, J.D.,P.E. Rankin Law Firm, PLLC 510 Ochiltree Street Nacogdoches, Texas 75961 Telephone: (936) 715-9333 Facsimile: (936) 715-9339 www.rankinlawfirm.com -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

Alex Deucher

15:14

New subject: RS600 still not working

2009/6/29 Dariem Pérez Herrera :

...

Alex Deucher escribió:

...
2009/6/26 Dariem Pérez Herrera :

...
I also attached my Xorg.0.log with -logverbose 7. I can see there are many functions been called which names suggest they are made for RS690, not RS600, so it is possible that MC cannot go idle because of this (incorrectly use of RS690 register addresses instead RS600 addresses). I'm not familiar with radeonhd source code, so trying to fix MC make me lost into the code ocean. Any mentorship or documentation available so I can try?

The radeon driver should have the correct bits for indirect MC access on RS690/740 and RS600. Note that RS690/740 and RS600 are different WRT MC setup. See: RADEONINMC() RADEONOUTMC() radeon_get_mc_idle() in radeon_driver.c for the relevant regs and bits.

Alex

Alex, What about the difference between MMIO register space used by radeon driver, and PCIe register space used by radeonhd? Is there any way to convert from the first to the second and vice-versa? Is it relevant at all?

I'm not sure the MC registers aliases in the pcie space work or not. As far as I know the index regs in MMIO space should be used. Note that the MC index regs live at different offsets in MMIO space for each chip family. Alex -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org

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Alex Deucher
Dariem Pérez Herrera
David C. Rankin
Matthias Hopf
Rafał Miłecki