https://bugzilla.suse.com/show_bug.cgi?id=1216194 https://bugzilla.suse.com/show_bug.cgi?id=1216194#c17 Jiri Slaby <jslaby@suse.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #17 from Jiri Slaby <jslaby@suse.com> --- It is possibly fixed by some of these commits: $ git log --oneline v6.5.6..v6.5.9 drivers/gpu/drm/i915/ 935df6cfa78a drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes Owned 2c9e90773fab drm/i915: Retry gtt fault when out of fence registers 1d61ce0a321f drm/i915: Register engines early to avoid type confusion 2f92524f5a7f drm/i915: Don't set PIPE_CONTROL_FLUSH_L3 for aux inval -- You are receiving this mail because: You are the assignee for the bug.