On Wed, Sep 28, 2022 at 09:12:43PM +0200, Michal Suchánek wrote:
Full disclosure, our company collaborated on further research to instrument a system and see if power optimisations could be written into gcc/a compiler. Initially it was an immense project, similar to "extracting a decagram of myelin from 4 tons of earth worms".
And do you have some data that you can share that shows which optimizarions save how much power for which workloads?
Sadly I don't think anything is as clear cut as that, but here's a link to Bristol Uni's research (courtesy of Embecosm stumping up the open access publication fee): https://doi.org/10.1093/comjnl/bxt129
That's exactly the thing I am missing here: some data showing the benefits of axing that hardware.
Because the same applies to power savings as applies to time savings - optimizing code you do not run at all or very rarely does not save you time nor power.
So far we only got some benchmark showing that compiling random pieces of code for x86-64-v3 runs mostly faster, and compiling some random pieces of code for x86-64-v2 runs sometimes faster and sometimes slower.
Whith no summary so it is not clear how often it runs faster, and how often it runs slower.
And it is not clear how often you will encounter such pieces of code in real world workloads, either.
There's always a chance that chip-feature X was hyper-specific to deep-pocketed customer Y and there is no general benefit. At least with RISC-V there'll be a ton of cryptic changelogs to grep through for the rationale. Daniel