Hello community, here is the log from the commit of package valgrind for openSUSE:Factory checked in at 2014-08-30 16:03:31 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/valgrind (Old) and /work/SRC/openSUSE:Factory/.valgrind.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Package is "valgrind" Changes: -------- --- /work/SRC/openSUSE:Factory/valgrind/valgrind.changes 2014-07-31 10:04:17.000000000 +0200 +++ /work/SRC/openSUSE:Factory/.valgrind.new/valgrind.changes 2014-08-30 16:03:35.000000000 +0200 @@ -1,0 +2,12 @@ +Sun Aug 17 21:46:19 UTC 2014 - dmueller@suse.com + +- update for ppc64le support (bnc#880334): + - drop: valgrind-3.9.0-merge.patches.from.Paul.McKenney.patch, + valgrind-3.9.0-ppc64le-abiv2.patch + + - add: VEX-r2803.diff, VEX-r2808.diff, VEX-r2816.diff + VEX-r2904.diff, VEX-r2910.diff, VEX-r2914.diff, VEX-r2915.diff, + VEX-r2916.diff, r13767.diff, r13770.diff, r14184.diff, r14238.diff, + r14239.diff, r14240.diff, r14246.diff + +------------------------------------------------------------------- Old: ---- valgrind-3.9.0-merge.patches.from.Paul.McKenney.patch valgrind-3.9.0-ppc64le-abiv2.patch New: ---- VEX-r2803.diff VEX-r2808.diff VEX-r2816.diff VEX-r2904.diff VEX-r2910.diff VEX-r2914.diff VEX-r2915.diff VEX-r2916.diff r13767.diff r13770.diff r14184.diff r14238.diff r14239.diff r14240.diff r14246.diff ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ valgrind.spec ++++++ --- /var/tmp/diff_new_pack.56OktI/_old 2014-08-30 16:03:37.000000000 +0200 +++ /var/tmp/diff_new_pack.56OktI/_new 2014-08-30 16:03:37.000000000 +0200 @@ -40,14 +40,28 @@ # svn di svn://svn.valgrind.org/vex/tags/VEX_3_5_0 svn://svn.valgrind.org/vex/branches/VEX_3_5_BRANCH > VEX_3_5_BRANCH.diff Patch1: jit-register-unregister.diff Patch2: armv6-support.diff -Patch3: valgrind-3.9.0-merge.patches.from.Paul.McKenney.patch -Patch4: valgrind-3.9.0-ppc64le-abiv2.patch +Patch3: r13767.diff +Patch4: r13770.diff Patch5: glibc-2.19.patch Patch6: r2798.diff Patch7: aarch64-support.diff Patch8: aarch64-VEX-support.diff Patch9: VEX-r2858.diff Patch10: valgrind-r13948.diff +# PPC64 LE support +Patch11: r14184.diff +Patch12: r14238.diff +Patch13: r14239.diff +Patch14: r14240.diff +Patch15: r14246.diff +Patch20: VEX-r2803.diff +Patch21: VEX-r2808.diff +Patch22: VEX-r2816.diff +Patch23: VEX-r2904.diff +Patch24: VEX-r2910.diff +Patch25: VEX-r2914.diff +Patch26: VEX-r2915.diff +Patch27: VEX-r2916.diff # during building the major version of glibc is built into the suppression file %define glibc_main_version %(getconf GNU_LIBC_VERSION | cut -d' ' -f2 | cut -d. -f1) %define glibc_major_version %(getconf GNU_LIBC_VERSION | cut -d' ' -f2 | cut -d. -f2) @@ -142,23 +156,44 @@ %prep %setup -q -n %{name}-%{version} -cd VEX %ifarch aarch64 +cd VEX %patch8 +cd .. %else %patch9 +%ifarch ppc64le +# PPC64LE +%patch20 +%patch21 +%patch22 +%patch23 +%patch24 +%patch25 +%patch26 +%patch27 +%endif %endif -cd .. %patch1 %ifarch aarch64 %patch7 %else %patch2 -%patch3 -p1 -%patch4 -p1 +%patch3 +%ifarch ppc64le +%patch4 +%endif %patch5 -p1 %patch6 %patch10 +%ifarch ppc64le +# PPC64LE +%patch11 +%patch12 +%patch13 +%patch14 +%patch15 +%endif %endif %build ++++++ VEX-r2803.diff ++++++ ++++ 21176 lines (skipped) ++++++ VEX-r2808.diff ++++++ --- VEX/priv/guest_ppc_toIR.c (Revision 2807) +++ VEX/priv/guest_ppc_toIR.c (Revision 2808) @@ -5233,6 +5233,7 @@ static Bool dis_int_ldst_mult ( UInt the Int simm16 = extend_s_16to32(uimm16); IRType ty = mode64 ? Ity_I64 : Ity_I32; + IROp mkAdd = mode64 ? Iop_Add64 : Iop_Add32; IRTemp EA = newTemp(ty); UInt r = 0; UInt ea_off = 0; @@ -5248,7 +5249,7 @@ static Bool dis_int_ldst_mult ( UInt the } DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); for (r = rD_addr; r <= 31; r++) { - irx_addr = binop(Iop_Add32, mkexpr(EA), mkU32(ea_off)); + irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); putIReg( r, mkWidenFrom32(ty, loadBE(Ity_I32, irx_addr ), False) ); ea_off += 4; @@ -5258,7 +5259,7 @@ static Bool dis_int_ldst_mult ( UInt the case 0x2F: // stmw (Store Multiple Word, PPC32 p527) DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); for (r = rS_addr; r <= 31; r++) { - irx_addr = binop(Iop_Add32, mkexpr(EA), mkU32(ea_off)); + irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); storeBE( irx_addr, mkNarrowTo32(ty, getIReg(r)) ); ea_off += 4; } ++++++ VEX-r2816.diff ++++++ --- VEX/priv/guest_ppc_toIR.c (Revision 2815) +++ VEX/priv/guest_ppc_toIR.c (Revision 2816) @@ -78,9 +78,9 @@ concerned) but have meaning for supporting Valgrind. A special instruction is flagged by a 16-byte preamble: - 32-bit mode: 54001800 54006800 5400E800 54009800 - (rlwinm 0,0,3,0,0; rlwinm 0,0,13,0,0; - rlwinm 0,0,29,0,0; rlwinm 0,0,19,0,0) + 32-bit mode: 5400183E 5400683E 5400E83E 5400983E + (rlwinm 0,0,3,0,31; rlwinm 0,0,13,0,31; + rlwinm 0,0,29,0,31; rlwinm 0,0,19,0,31) 64-bit mode: 78001800 78006800 7800E802 78009802 (rotldi 0,0,3; rotldi 0,0,13; @@ -18523,20 +18523,20 @@ DisResult disInstr_PPC_WRK ( UChar* code = (UChar*)(guest_code + delta); /* Spot the 16-byte preamble: 32-bit mode: - 54001800 rlwinm 0,0,3,0,0 - 54006800 rlwinm 0,0,13,0,0 - 5400E800 rlwinm 0,0,29,0,0 - 54009800 rlwinm 0,0,19,0,0 + 5400183E rlwinm 0,0,3,0,31 + 5400683E rlwinm 0,0,13,0,31 + 5400E83E rlwinm 0,0,29,0,31 + 5400983E rlwinm 0,0,19,0,31 64-bit mode: 78001800 rotldi 0,0,3 78006800 rotldi 0,0,13 7800E802 rotldi 0,0,61 78009802 rotldi 0,0,51 */ - UInt word1 = mode64 ? 0x78001800 : 0x54001800; - UInt word2 = mode64 ? 0x78006800 : 0x54006800; - UInt word3 = mode64 ? 0x7800E802 : 0x5400E800; - UInt word4 = mode64 ? 0x78009802 : 0x54009800; + UInt word1 = mode64 ? 0x78001800 : 0x5400183E; + UInt word2 = mode64 ? 0x78006800 : 0x5400683E; + UInt word3 = mode64 ? 0x7800E802 : 0x5400E83E; + UInt word4 = mode64 ? 0x78009802 : 0x5400983E; if (getUIntBigendianly(code+ 0) == word1 && getUIntBigendianly(code+ 4) == word2 && getUIntBigendianly(code+ 8) == word3 && ++++++ VEX-r2858.diff ++++++ --- /var/tmp/diff_new_pack.56OktI/_old 2014-08-30 16:03:37.000000000 +0200 +++ /var/tmp/diff_new_pack.56OktI/_new 2014-08-30 16:03:37.000000000 +0200 @@ -8,11 +8,11 @@ for CALL (E8,FF/2), RET (C2,C3), JMP (EB,E9,FF/4) and Jcc (70-7F,0F 80-8F). All new MPX instructions are currently NOPs and the bnd prefix is ignored. ------------------------------------------------------------------------ -Index: priv/guest_amd64_toIR.c +Index: VEX/priv/guest_amd64_toIR.c =================================================================== ---- priv/guest_amd64_toIR.c (revision 2857) -+++ priv/guest_amd64_toIR.c (revision 2858) -@@ -767,10 +767,10 @@ static Bool have66orF2orF3 ( Prefix pfx +--- VEX/priv/guest_amd64_toIR.c.orig ++++ VEX/priv/guest_amd64_toIR.c +@@ -771,10 +771,10 @@ static Bool have66orF2orF3 ( Prefix pfx return toBool( ! haveNo66noF2noF3(pfx) ); } @@ -26,7 +26,7 @@ } /* Clear all the segment-override bits in a prefix. */ -@@ -4266,8 +4266,12 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, +@@ -4270,8 +4270,12 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, modrm = getUChar(delta); if (epartIsReg(modrm)) { @@ -41,7 +41,7 @@ assign(t1, getIRegE(sz,pfx,modrm)); switch (gregLO3ofRM(modrm)) { case 0: /* INC */ -@@ -4287,6 +4291,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, +@@ -4291,6 +4295,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, case 2: /* call Ev */ /* Ignore any sz value and operate as if sz==8. */ if (!(sz == 4 || sz == 8)) goto unhandledR; @@ -49,7 +49,7 @@ sz = 8; t3 = newTemp(Ity_I64); assign(t3, getIRegE(sz,pfx,modrm)); -@@ -4302,6 +4307,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, +@@ -4306,6 +4311,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, case 4: /* jmp Ev */ /* Ignore any sz value and operate as if sz==8. */ if (!(sz == 4 || sz == 8)) goto unhandledR; @@ -57,7 +57,7 @@ sz = 8; t3 = newTemp(Ity_I64); assign(t3, getIRegE(sz,pfx,modrm)); -@@ -4334,11 +4340,14 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, +@@ -4338,11 +4344,14 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, showSz ? nameISize(sz) : ' ', nameIRegE(sz, pfx, modrm)); } else { @@ -73,7 +73,7 @@ } if (!validF2orF3) goto unhandledM; /* */ -@@ -4375,6 +4384,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, +@@ -4379,6 +4388,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, case 2: /* call Ev */ /* Ignore any sz value and operate as if sz==8. */ if (!(sz == 4 || sz == 8)) goto unhandledM; @@ -81,7 +81,7 @@ sz = 8; t3 = newTemp(Ity_I64); assign(t3, loadLE(Ity_I64,mkexpr(addr))); -@@ -4390,6 +4400,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, +@@ -4394,6 +4404,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, case 4: /* JMP Ev */ /* Ignore any sz value and operate as if sz==8. */ if (!(sz == 4 || sz == 8)) goto unhandledM; @@ -89,7 +89,7 @@ sz = 8; t3 = newTemp(Ity_I64); assign(t3, loadLE(Ity_I64,mkexpr(addr))); -@@ -19716,7 +19727,8 @@ Long dis_ESC_NONE ( +@@ -19550,7 +19561,8 @@ Long dis_ESC_NONE ( case 0x7F: { /* JGb/JNLEb (jump greater) */ Long jmpDelta; const HChar* comment = ""; @@ -99,7 +99,7 @@ jmpDelta = getSDisp8(delta); vassert(-128 <= jmpDelta && jmpDelta < 128); d64 = (guest_RIP_bbstart+delta+1) + jmpDelta; -@@ -20369,7 +20381,8 @@ Long dis_ESC_NONE ( +@@ -20203,7 +20215,8 @@ Long dis_ESC_NONE ( } case 0xC2: /* RET imm16 */ @@ -109,7 +109,7 @@ d64 = getUDisp16(delta); delta += 2; dis_ret(dres, vbi, d64); -@@ -20377,8 +20390,9 @@ Long dis_ESC_NONE ( +@@ -20211,8 +20224,9 @@ Long dis_ESC_NONE ( return delta; case 0xC3: /* RET */ @@ -120,7 +120,7 @@ dis_ret(dres, vbi, 0); DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n"); return delta; -@@ -20782,7 +20796,8 @@ Long dis_ESC_NONE ( +@@ -20606,7 +20620,8 @@ Long dis_ESC_NONE ( } case 0xE8: /* CALL J4 */ @@ -130,7 +130,7 @@ d64 = getSDisp32(delta); delta += 4; d64 += (guest_RIP_bbstart+delta); /* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */ -@@ -20805,9 +20820,10 @@ Long dis_ESC_NONE ( +@@ -20629,9 +20644,10 @@ Long dis_ESC_NONE ( return delta; case 0xE9: /* Jv (jump, 16/32 offset) */ @@ -142,7 +142,7 @@ d64 = (guest_RIP_bbstart+delta+sz) + getSDisp(sz,delta); delta += sz; if (resteerOkFn(callback_opaque,d64)) { -@@ -20821,9 +20837,10 @@ Long dis_ESC_NONE ( +@@ -20645,9 +20661,10 @@ Long dis_ESC_NONE ( return delta; case 0xEB: /* Jb (jump, byte offset) */ @@ -154,7 +154,7 @@ d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta); delta++; if (resteerOkFn(callback_opaque,d64)) { -@@ -21241,7 +21258,8 @@ Long dis_ESC_0F ( +@@ -21065,7 +21082,8 @@ Long dis_ESC_0F ( case 0x8F: { /* JGb/JNLEb (jump greater) */ Long jmpDelta; const HChar* comment = ""; @@ -164,7 +164,7 @@ jmpDelta = getSDisp32(delta); d64 = (guest_RIP_bbstart+delta+4) + jmpDelta; delta += 4; -@@ -21332,6 +21350,66 @@ Long dis_ESC_0F ( +@@ -21156,6 +21174,66 @@ Long dis_ESC_0F ( } return delta; ++++++ VEX-r2904.diff ++++++ Index: VEX/priv/host_ppc_isel.c =================================================================== --- VEX/priv/host_ppc_isel.c.orig +++ VEX/priv/host_ppc_isel.c @@ -704,12 +704,6 @@ void doHelperCall ( /*OUT*/UInt* stack UInt nVECRETs = 0; UInt nBBPTRs = 0; - /* Do we need to force use of an odd-even reg pair for 64-bit args? - JRS 31-07-2013: is this still relevant, now that we are not - generating code for 32-bit AIX ? */ - Bool regalign_int64s - = (!mode64) && env->vbi->host_ppc32_regalign_int64_args; - /* Marshal args for a call and do the call. This function only deals with a tiny set of possibilities, which @@ -867,7 +861,7 @@ void doHelperCall ( /*OUT*/UInt* stack iselWordExpr_R(env, arg) )); } else { // Ity_I64 in 32-bit mode HReg rHi, rLo; - if (regalign_int64s && (argreg%2) == 1) + if ((argreg%2) == 1) // ppc32 ELF abi spec for passing LONG_LONG argreg++; // XXX: odd argreg => even rN vassert(argreg < PPC_N_REGPARMS-1); @@ -943,7 +937,7 @@ void doHelperCall ( /*OUT*/UInt* stack tmpregs[argreg] = iselWordExpr_R(env, arg); } else { // Ity_I64 in 32-bit mode HReg rHi, rLo; - if (regalign_int64s && (argreg%2) == 1) + if ((argreg%2) == 1) // ppc32 ELF abi spec for passing LONG_LONG argreg++; // XXX: odd argreg => even rN vassert(argreg < PPC_N_REGPARMS-1); Index: VEX/priv/guest_ppc_toIR.c =================================================================== --- VEX/priv/guest_ppc_toIR.c.orig +++ VEX/priv/guest_ppc_toIR.c @@ -6060,9 +6060,7 @@ static Bool dis_syslink ( UInt theInstr, /* It's important that all ArchRegs carry their up-to-date value at this point. So we declare an end-of-block here, which forces any TempRegs caching ArchRegs to be flushed. */ - putGST( PPC_GST_CIA, abiinfo->guest_ppc_sc_continues_at_LR - ? getGST( PPC_GST_LR ) - : mkSzImm( ty, nextInsnAddr() )); + putGST( PPC_GST_CIA, mkSzImm( ty, nextInsnAddr() )); dres->whatNext = Dis_StopHere; dres->jk_StopHere = Ijk_Sys_syscall; Index: VEX/priv/main_main.c =================================================================== --- VEX/priv/main_main.c.orig +++ VEX/priv/main_main.c @@ -1242,9 +1242,7 @@ void LibVEX_default_VexAbiInfo ( /*OUT*/ vbi->guest_amd64_assume_gs_is_0x60 = False; vbi->guest_ppc_zap_RZ_at_blr = False; vbi->guest_ppc_zap_RZ_at_bl = NULL; - vbi->guest_ppc_sc_continues_at_LR = False; vbi->host_ppc_calls_use_fndescrs = False; - vbi->host_ppc32_regalign_int64_args = False; } Index: VEX/pub/libvex.h =================================================================== --- VEX/pub/libvex.h.orig +++ VEX/pub/libvex.h @@ -291,8 +291,6 @@ void LibVEX_default_VexArchInfo ( /*OUT* guest_stack_redzone_size guest is ppc32-linux ==> 0 guest is ppc64-linux ==> 288 - guest is ppc32-aix5 ==> 220 - guest is ppc64-aix5 ==> unknown guest is amd64-linux ==> 128 guest is other ==> inapplicable @@ -309,32 +307,16 @@ void LibVEX_default_VexArchInfo ( /*OUT* guest_ppc_zap_RZ_at_blr guest is ppc64-linux ==> True guest is ppc32-linux ==> False - guest is ppc64-aix5 ==> unknown - guest is ppc32-aix5 ==> False guest is other ==> inapplicable guest_ppc_zap_RZ_at_bl guest is ppc64-linux ==> const True guest is ppc32-linux ==> const False - guest is ppc64-aix5 ==> unknown - guest is ppc32-aix5 ==> True except for calls to - millicode, $SAVEFn, $RESTFn - guest is other ==> inapplicable - - guest_ppc_sc_continues_at_LR: - guest is ppc32-aix5 or ppc64-aix5 ==> True - guest is ppc32-linux or ppc64-linux ==> False guest is other ==> inapplicable host_ppc_calls_use_fndescrs: host is ppc32-linux ==> False host is ppc64-linux ==> True - host is ppc32-aix5 or ppc64-aix5 ==> True - host is other ==> inapplicable - - host_ppc32_regalign_int64_args: - host is ppc32-linux ==> True - host is ppc32-aix5 ==> False host is other ==> inapplicable */ @@ -364,20 +346,10 @@ typedef is assumed equivalent to a fn which always returns False. */ Bool (*guest_ppc_zap_RZ_at_bl)(Addr64); - /* PPC32/PPC64 GUESTS only: where does the kernel resume after - 'sc'? False => Linux style, at the next insn. True => AIX - style, at the address stated in the link register. */ - Bool guest_ppc_sc_continues_at_LR; - /* PPC32/PPC64 HOSTS only: does '&f' give us a pointer to a function descriptor on the host, or to the function code itself? True => descriptor, False => code. */ Bool host_ppc_calls_use_fndescrs; - - /* PPC32 HOSTS only: when generating code to pass a 64-bit value - (actual parameter) in a pair of regs, should we skip an arg - reg if it is even-numbered? True => yes, False => no. */ - Bool host_ppc32_regalign_int64_args; } VexAbiInfo; ++++++ VEX-r2910.diff ++++++ ++++ 2010 lines (skipped) ++++++ VEX-r2914.diff ++++++ ++++ 7306 lines (skipped) ++++++ VEX-r2915.diff ++++++ Index: VEX/priv/guest_ppc_toIR.c =================================================================== --- VEX/priv/guest_ppc_toIR.c.orig +++ VEX/priv/guest_ppc_toIR.c @@ -20134,6 +20134,7 @@ DisResult disInstr_PPC ( IRSB* ir dres.whatNext = Dis_StopHere; dres.jk_StopHere = Ijk_NoDecode; dres.len = 0; + dis.continueAt = 0; return dres; } ++++++ VEX-r2916.diff ++++++ Index: VEX/priv/guest_ppc_toIR.c =================================================================== --- VEX/priv/guest_ppc_toIR.c.orig +++ VEX/priv/guest_ppc_toIR.c @@ -20134,7 +20134,7 @@ DisResult disInstr_PPC ( IRSB* ir dres.whatNext = Dis_StopHere; dres.jk_StopHere = Ijk_NoDecode; dres.len = 0; - dis.continueAt = 0; + dres.continueAt = 0; return dres; } ++++++ r13767.diff ++++++ ------------------------------------------------------------------------ r13767 | dejanj | 2013-12-27 10:06:55 +0100 (Fr, 27. Dez 2013) | 4 Zeilen mips32: Adding mips32/Android support to Valgrind. Necessary changes to Valgrind to support mips32 on Android. ------------------------------------------------------------------------ Index: coregrind/vg_preloaded.c =================================================================== --- coregrind/vg_preloaded.c.orig +++ coregrind/vg_preloaded.c @@ -57,7 +57,8 @@ void VG_NOTIFY_ON_LOAD(freeres)( void ); void VG_NOTIFY_ON_LOAD(freeres)( void ) { # if !defined(__UCLIBC__) \ - && !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) + && !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) extern void __libc_freeres(void); __libc_freeres(); # endif Index: coregrind/m_options.c =================================================================== --- coregrind/m_options.c.orig +++ coregrind/m_options.c @@ -47,7 +47,8 @@ VexControl VG_(clo_vex_control); Bool VG_(clo_error_limit) = True; Int VG_(clo_error_exitcode) = 0; -#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) VgVgdb VG_(clo_vgdb) = Vg_VgdbNo; // currently disabled on Android #else VgVgdb VG_(clo_vgdb) = Vg_VgdbYes; Index: coregrind/vgdb.c =================================================================== --- coregrind/vgdb.c.orig +++ coregrind/vgdb.c @@ -1643,7 +1643,8 @@ void received_signal (int signum) sigpipe++; } else if (signum == SIGALRM) { sigalrm++; -#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) /* Android has no pthread_cancel. As it also does not have PTRACE_INVOKER, there is no need for cleanup action. So, we just do nothing. */ Index: coregrind/m_replacemalloc/vg_replace_malloc.c =================================================================== --- coregrind/m_replacemalloc/vg_replace_malloc.c.orig +++ coregrind/m_replacemalloc/vg_replace_malloc.c @@ -116,7 +116,7 @@ __attribute__ ((__noreturn__)) static inline void my_exit ( int x ) { -# if defined(VGPV_arm_linux_android) +# if defined(VGPV_arm_linux_android) || defined(VGPV_mips32_linux_android) __asm__ __volatile__(".word 0xFFFFFFFF"); while (1) {} # elif defined(VGPV_x86_linux_android) @@ -131,7 +131,8 @@ static inline void my_exit ( int x ) /* Same problem with getpagesize. */ static inline int my_getpagesize ( void ) { -# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) return 4096; /* kludge - link failure on Android, for some reason */ # else extern int getpagesize (void); @@ -939,7 +940,8 @@ static inline void trigger_memcheck_erro MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_usable_size); MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, malloc_size); MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_size); -# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, dlmalloc_usable_size); MALLOC_USABLE_SIZE(SO_SYN_MALLOC, dlmalloc_usable_size); # endif Index: coregrind/m_coredump/coredump-elf.c =================================================================== --- coregrind/m_coredump/coredump-elf.c.orig +++ coregrind/m_coredump/coredump-elf.c @@ -136,7 +136,8 @@ static void fill_phdr(ESZ(Phdr) *phdr, c phdr->p_align = VKI_PAGE_SIZE; } -#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) /* Android's libc doesn't provide a definition for this. Hence: */ typedef struct { @@ -159,7 +160,8 @@ static UInt note_size(const struct note + VG_ROUNDUP(n->note.n_descsz, 4); } -#if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) +#if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) static void add_note(struct note **list, const HChar *name, UInt type, const void *data, UInt datasz) { @@ -605,7 +607,8 @@ void make_elf_coredump(ThreadId tid, con continue; # if defined(VGP_x86_linux) -# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) +# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) { vki_elf_fpxregset_t xfpu; fill_xfpu(&VG_(threads)[i], &xfpu); @@ -615,18 +618,21 @@ void make_elf_coredump(ThreadId tid, con # endif fill_fpu(&VG_(threads)[i], &fpu); -# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) +# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) add_note(¬elist, "CORE", NT_FPREGSET, &fpu, sizeof(fpu)); # endif fill_prstatus(&VG_(threads)[i], &prstatus, si); -# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) +# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) add_note(¬elist, "CORE", NT_PRSTATUS, &prstatus, sizeof(prstatus)); # endif } fill_prpsinfo(&VG_(threads)[tid], &prpsinfo); -# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) +# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) add_note(¬elist, "CORE", NT_PRPSINFO, &prpsinfo, sizeof(prpsinfo)); # endif Index: coregrind/m_ume/main.c =================================================================== --- coregrind/m_ume/main.c.orig +++ coregrind/m_ume/main.c @@ -199,7 +199,8 @@ static Bool is_binary_file(const HChar* // will refuse to (eg. scripts lacking a "#!" prefix). static Int do_exec_shell_followup(Int ret, const HChar* exe_name, ExeInfo* info) { -# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) const HChar* default_interp_name = "/system/bin/sh"; # else const HChar* default_interp_name = "/bin/sh"; Index: coregrind/m_syswrap/syswrap-linux.c =================================================================== --- coregrind/m_syswrap/syswrap-linux.c.orig +++ coregrind/m_syswrap/syswrap-linux.c @@ -6764,7 +6764,8 @@ PRE(sys_ioctl) /* These just take an int by value */ break; -# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) /* ashmem */ case VKI_ASHMEM_GET_SIZE: case VKI_ASHMEM_SET_SIZE: @@ -6957,7 +6958,8 @@ POST(sys_ioctl) /* --- BEGIN special IOCTL handlers for specific Android hardware --- */ -# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) # if defined(ANDROID_HARDWARE_nexus_s) @@ -7875,7 +7877,8 @@ POST(sys_ioctl) } break; -# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) /* ashmem */ case VKI_ASHMEM_GET_SIZE: case VKI_ASHMEM_SET_SIZE: Index: coregrind/m_syswrap/syswrap-main.c =================================================================== --- coregrind/m_syswrap/syswrap-main.c.orig +++ coregrind/m_syswrap/syswrap-main.c @@ -467,7 +467,15 @@ void getSyscallArgsFromGuestState ( /*OU #elif defined(VGP_mips32_linux) VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla; canonical->sysno = gst->guest_r2; // v0 - if (canonical->sysno != __NR_syscall) { + if (canonical->sysno == __NR_exit) { + canonical->arg1 = gst->guest_r4; // a0 + canonical->arg2 = 0; + canonical->arg3 = 0; + canonical->arg4 = 0; + canonical->arg5 = 0; + canonical->arg6 = 0; + canonical->arg8 = 0; + } else if (canonical->sysno != __NR_syscall) { canonical->arg1 = gst->guest_r4; // a0 canonical->arg2 = gst->guest_r5; // a1 canonical->arg3 = gst->guest_r6; // a2 Index: coregrind/m_initimg/initimg-linux.c =================================================================== --- coregrind/m_initimg/initimg-linux.c.orig +++ coregrind/m_initimg/initimg-linux.c @@ -640,7 +640,9 @@ Addr setup_client_stack( void* init_sp, case AT_GID: case AT_EGID: case AT_CLKTCK: -# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) +# if !defined(VGPV_arm_linux_android) \ + && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) case AT_FPUCW: /* missing on android */ # endif /* All these are pointerless, so we don't need to do @@ -670,7 +672,8 @@ Addr setup_client_stack( void* init_sp, So, keep the AT_BASE on android for now. ??? Need to dig in depth about AT_BASE/GDB interaction */ # if !defined(VGPV_arm_linux_android) \ - && !defined(VGPV_x86_linux_android) + && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) auxv->a_type = AT_IGNORE; # endif auxv->u.a_val = info->interp_base; Index: coregrind/m_debuginfo/readstabs.c =================================================================== --- coregrind/m_debuginfo/readstabs.c.orig +++ coregrind/m_debuginfo/readstabs.c @@ -36,7 +36,8 @@ /* "on Linux (except android), or on Darwin" */ #if (defined(VGO_linux) && \ - !(defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)) \ + !(defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android)) \ || defined(VGO_darwin)) #include "pub_core_basics.h" Index: coregrind/launcher-linux.c =================================================================== --- coregrind/launcher-linux.c.orig +++ coregrind/launcher-linux.c @@ -222,7 +222,9 @@ static const char *select_platform(const platform = "mips64-linux"; } } else if (header[EI_DATA] == ELFDATA2MSB) { -# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) +# if !defined(VGPV_arm_linux_android) \ + && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) if (ehdr->e_machine == EM_PPC64 && (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { Index: include/vki/vki-linux.h =================================================================== --- include/vki/vki-linux.h.orig +++ include/vki/vki-linux.h @@ -2865,7 +2865,8 @@ struct vki_getcpu_cache { // From kernel/common/include/linux/ashmem.h //---------------------------------------------------------------------- -#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) +#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ + || defined(VGPV_mips32_linux_android) #define VKI_ASHMEM_NAME_LEN 256 Index: configure.ac =================================================================== --- configure.ac.orig +++ configure.ac @@ -957,9 +957,9 @@ DEFAULT_SUPP="exp-sgcheck.supp ${DEFAULT # Normally the PLAT = (ARCH, OS) characterisation of the platform is enough. # But there are times where we need a bit more control. The motivating # and currently only case is Android: this is almost identical to -# {x86,arm}-linux, but not quite. So this introduces the concept of platform -# variant tags, which get passed in the compile as -DVGPV_<arch>_<os>_<variant> -# along with the main -DVGP_<arch>_<os> definition. +# {x86,arm,mips}-linux, but not quite. So this introduces the concept of +# platform variant tags, which get passed in the compile as +# -DVGPV_<arch>_<os>_<variant> along with the main -DVGP_<arch>_<os> definition. # # In almost all cases, the <variant> bit is "vanilla". But for Android # it is "android" instead. Index: README.android =================================================================== --- README.android.orig +++ README.android @@ -13,6 +13,12 @@ ARM: x86: Android 4.0.3 running on android x86 emulator. +mips32: + Android 4.1.2 running on android mips emulator. + Android 4.2.2 running on android mips emulator. + Android 4.3 running on android mips emulator. + Android 4.0.4 running on BROADCOM bcm7425 + On android-arm, GDBserver might insert breaks at wrong addresses. Feedback on this welcome. @@ -70,6 +76,10 @@ export AR=$NDKROOT/toolchains/x86-4.4.3/ export LD=$NDKROOT/toolchains/x86-4.4.3/prebuilt/linux-x86/bin/i686-android-linux-ld export CC=$NDKROOT/toolchains/x86-4.4.3/prebuilt/linux-x86/bin/i686-android-linux-gcc +# For MIPS32 +export AR=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-ar +export LD=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-ld +export CC=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-gcc # Do configuration stuff. Don't mess with the --prefix in the # configure command below, even if you think it's wrong. @@ -97,6 +107,13 @@ CPPFLAGS="--sysroot=$NDKROOT/platforms/a --host=i686-android-linux --target=i686-android-linux \ --with-tmpdir=/sdcard +# for MIPS32 +CPPFLAGS="--sysroot=$NDKROOT/platforms/android-18/arch-mips -DANDROID_HARDWARE_$HWKIND" \ + CFLAGS="--sysroot=$NDKROOT/platforms/android-18/arch-mips" \ + ./configure --prefix=/data/local/Inst \ + --host=mipsel-linux-android --target=mipsel-linux-android \ + --with-tmpdir=/sdcard + # At the end of the configure run, a few lines of details # are printed. Make sure that you see these two lines: # @@ -108,6 +125,10 @@ CPPFLAGS="--sysroot=$NDKROOT/platforms/a # Platform variant: android # Primary -DVGPV string: -DVGPV_x86_linux_android=1 # +# For mips32: +# Platform variant: android +# Primary -DVGPV string: -DVGPV_mips32_linux_android=1 +# # If you see anything else at this point, something is wrong, and # either the build will fail, or will succeed but you'll get something # which won't work. ++++++ r13770.diff ++++++ ++++ 6551 lines (skipped) ++++++ r14184.diff ++++++ ------------------------------------------------------------------------ r14184 | sewardj | 2014-07-24 14:45:24 +0200 (Do, 24. Jul 2014) | 8 Zeilen Track vex r2910 (infrastructural improvements in representation of endianness in VEX). In short: in m_machine.c, VG_(machine_get_hwcaps), get the endianness of the host, and pass it through to all places (in VEX) where it is required. ------------------------------------------------------------------------ Index: coregrind/m_transtab.c =================================================================== --- coregrind/m_transtab.c.orig +++ coregrind/m_transtab.c @@ -747,8 +747,11 @@ void VG_(tt_tc_do_chaining) ( void* from Bool to_fastEP ) { /* Get the CPU info established at startup. */ - VexArch vex_arch = VexArch_INVALID; - VG_(machine_get_VexArchInfo)( &vex_arch, NULL ); + VexArch arch_host = VexArch_INVALID; + VexArchInfo archinfo_host; + VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host)); + VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host ); + VexEndness endness_host = archinfo_host.endness; // host_code is where we're patching to. So it needs to // take into account, whether we're jumping to the slow @@ -757,7 +760,8 @@ void VG_(tt_tc_do_chaining) ( void* from // the slow (tcptr) entry point. TTEntry* to_tte = index_tte(to_sNo, to_tteNo); void* host_code = ((UChar*)to_tte->tcptr) - + (to_fastEP ? LibVEX_evCheckSzB(vex_arch) : 0); + + (to_fastEP ? LibVEX_evCheckSzB(arch_host, + endness_host) : 0); // stay sane -- the patch point (dst) is in this sector's code cache vg_assert( (UChar*)host_code >= (UChar*)sectors[to_sNo].tc ); @@ -789,7 +793,7 @@ void VG_(tt_tc_do_chaining) ( void* from since it is host-dependent. */ VexInvalRange vir = LibVEX_Chain( - vex_arch, + arch_host, endness_host, from__patch_addr, VG_(fnptr_to_fnentry)( to_fastEP ? &VG_(disp_cp_chain_me_to_fastEP) @@ -833,7 +837,7 @@ void VG_(tt_tc_do_chaining) ( void* from addresses of the destination block (that is, the block that owns this InEdge). */ __attribute__((noinline)) -static void unchain_one ( VexArch vex_arch, +static void unchain_one ( VexArch arch_host, VexEndness endness_host, InEdge* ie, void* to_fastEPaddr, void* to_slowEPaddr ) { @@ -858,7 +862,7 @@ static void unchain_one ( VexArch vex_ar // place_to_jump_to_EXPECTED really is the current dst, and // asserts if it isn't. VexInvalRange vir - = LibVEX_UnChain( vex_arch, place_to_patch, + = LibVEX_UnChain( arch_host, endness_host, place_to_patch, place_to_jump_to_EXPECTED, disp_cp_chain_me ); VG_(invalidate_icache)( (void*)vir.start, vir.len ); } @@ -868,13 +872,14 @@ static void unchain_one ( VexArch vex_ar succs of its associated blocks accordingly. This includes undoing any chained jumps to this block. */ static -void unchain_in_preparation_for_deletion ( VexArch vex_arch, +void unchain_in_preparation_for_deletion ( VexArch arch_host, + VexEndness endness_host, UInt here_sNo, UInt here_tteNo ) { if (DEBUG_TRANSTAB) VG_(printf)("QQQ unchain_in_prep %u.%u...\n", here_sNo, here_tteNo); UWord i, j, n, m; - Int evCheckSzB = LibVEX_evCheckSzB(vex_arch); + Int evCheckSzB = LibVEX_evCheckSzB(arch_host, endness_host); TTEntry* here_tte = index_tte(here_sNo, here_tteNo); if (DEBUG_TRANSTAB) VG_(printf)("... QQQ tt.entry 0x%llu tt.tcptr 0x%p\n", @@ -888,7 +893,7 @@ void unchain_in_preparation_for_deletion // Undo the chaining. UChar* here_slow_EP = (UChar*)here_tte->tcptr; UChar* here_fast_EP = here_slow_EP + evCheckSzB; - unchain_one(vex_arch, ie, here_fast_EP, here_slow_EP); + unchain_one(arch_host, endness_host, ie, here_fast_EP, here_slow_EP); // Find the corresponding entry in the "from" node's out_edges, // and remove it. TTEntry* from_tte = index_tte(ie->from_sNo, ie->from_tteNo); @@ -1427,8 +1432,11 @@ static void initialiseSector ( Int sno ) vg_assert(sec->tc_next != NULL); n_dump_count += sec->tt_n_inuse; - VexArch vex_arch = VexArch_INVALID; - VG_(machine_get_VexArchInfo)( &vex_arch, NULL ); + VexArch arch_host = VexArch_INVALID; + VexArchInfo archinfo_host; + VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host)); + VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host ); + VexEndness endness_host = archinfo_host.endness; /* Visit each just-about-to-be-abandoned translation. */ if (DEBUG_TRANSTAB) VG_(printf)("QQQ unlink-entire-sector: %d START\n", @@ -1444,7 +1452,8 @@ static void initialiseSector ( Int sno ) sec->tt[i].entry, sec->tt[i].vge ); } - unchain_in_preparation_for_deletion(vex_arch, sno, i); + unchain_in_preparation_for_deletion(arch_host, + endness_host, sno, i); } else { vg_assert(sec->tt[i].n_tte2ec == 0); } @@ -1508,8 +1517,7 @@ void VG_(add_to_transtab)( VexGuestExten UInt code_len, Bool is_self_checking, Int offs_profInc, - UInt n_guest_instrs, - VexArch arch_host ) + UInt n_guest_instrs ) { Int tcAvailQ, reqdQ, y, i; ULong *tcptr, *tcptr2; @@ -1627,8 +1635,13 @@ void VG_(add_to_transtab)( VexGuestExten /* Patch in the profile counter location, if necessary. */ if (offs_profInc != -1) { vg_assert(offs_profInc >= 0 && offs_profInc < code_len); + VexArch arch_host = VexArch_INVALID; + VexArchInfo archinfo_host; + VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host)); + VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host ); + VexEndness endness_host = archinfo_host.endness; VexInvalRange vir - = LibVEX_PatchProfInc( arch_host, + = LibVEX_PatchProfInc( arch_host, endness_host, dstP + offs_profInc, §ors[y].tt[i].count ); VG_(invalidate_icache)( (void*)vir.start, vir.len ); @@ -1775,7 +1788,7 @@ Bool overlaps ( Addr64 start, ULong rang /* Delete a tt entry, and update all the eclass data accordingly. */ static void delete_tte ( /*MOD*/Sector* sec, UInt secNo, Int tteno, - VexArch vex_arch ) + VexArch arch_host, VexEndness endness_host ) { Int i, ec_num, ec_idx; TTEntry* tte; @@ -1789,7 +1802,7 @@ static void delete_tte ( /*MOD*/Sector* vg_assert(tte->n_tte2ec >= 1 && tte->n_tte2ec <= 3); /* Unchain .. */ - unchain_in_preparation_for_deletion(vex_arch, secNo, tteno); + unchain_in_preparation_for_deletion(arch_host, endness_host, secNo, tteno); /* Deal with the ec-to-tte links first. */ for (i = 0; i < tte->n_tte2ec; i++) { @@ -1829,7 +1842,8 @@ static Bool delete_translations_in_sector_eclass ( /*MOD*/Sector* sec, UInt secNo, Addr64 guest_start, ULong range, Int ec, - VexArch vex_arch ) + VexArch arch_host, + VexEndness endness_host ) { Int i; UShort tteno; @@ -1853,7 +1867,7 @@ Bool delete_translations_in_sector_eclas if (overlaps( guest_start, range, &tte->vge )) { anyDeld = True; - delete_tte( sec, secNo, (Int)tteno, vex_arch ); + delete_tte( sec, secNo, (Int)tteno, arch_host, endness_host ); } } @@ -1868,7 +1882,8 @@ Bool delete_translations_in_sector_eclas static Bool delete_translations_in_sector ( /*MOD*/Sector* sec, UInt secNo, Addr64 guest_start, ULong range, - VexArch vex_arch ) + VexArch arch_host, + VexEndness endness_host ) { Int i; Bool anyDeld = False; @@ -1877,7 +1892,7 @@ Bool delete_translations_in_sector ( /*M if (sec->tt[i].status == InUse && overlaps( guest_start, range, &sec->tt[i].vge )) { anyDeld = True; - delete_tte( sec, secNo, i, vex_arch ); + delete_tte( sec, secNo, i, arch_host, endness_host ); } } @@ -1907,8 +1922,11 @@ void VG_(discard_translations) ( Addr64 if (range == 0) return; - VexArch vex_arch = VexArch_INVALID; - VG_(machine_get_VexArchInfo)( &vex_arch, NULL ); + VexArch arch_host = VexArch_INVALID; + VexArchInfo archinfo_host; + VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host)); + VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host ); + VexEndness endness_host = archinfo_host.endness; /* There are two different ways to do this. @@ -1950,11 +1968,11 @@ void VG_(discard_translations) ( Addr64 continue; anyDeleted |= delete_translations_in_sector_eclass( sec, sno, guest_start, range, ec, - vex_arch + arch_host, endness_host ); anyDeleted |= delete_translations_in_sector_eclass( sec, sno, guest_start, range, ECLASS_MISC, - vex_arch + arch_host, endness_host ); } @@ -1970,7 +1988,9 @@ void VG_(discard_translations) ( Addr64 if (sec->tc == NULL) continue; anyDeleted |= delete_translations_in_sector( - sec, sno, guest_start, range, vex_arch ); + sec, sno, guest_start, range, + arch_host, endness_host + ); } } Index: coregrind/m_main.c =================================================================== --- coregrind/m_main.c.orig +++ coregrind/m_main.c @@ -1391,9 +1391,10 @@ static void print_preamble ( Bool loggin VG_(machine_get_VexArchInfo)( &vex_arch, &vex_archinfo ); VG_(message)( Vg_DebugMsg, - "Arch and hwcaps: %s, %s\n", - LibVEX_ppVexArch ( vex_arch ), - LibVEX_ppVexHwCaps ( vex_arch, vex_archinfo.hwcaps ) + "Arch and hwcaps: %s, %s, %s\n", + LibVEX_ppVexArch ( vex_arch ), + LibVEX_ppVexEndness ( vex_archinfo.endness ), + LibVEX_ppVexHwCaps ( vex_arch, vex_archinfo.hwcaps ) ); VG_(message)( Vg_DebugMsg, Index: coregrind/pub_core_transtab.h =================================================================== --- coregrind/pub_core_transtab.h.orig +++ coregrind/pub_core_transtab.h @@ -83,8 +83,7 @@ void VG_(add_to_transtab)( VexGuestExten UInt code_len, Bool is_self_checking, Int offs_profInc, - UInt n_guest_instrs, - VexArch arch_host ); + UInt n_guest_instrs ); extern void VG_(tt_tc_do_chaining) ( void* from__patch_addr, Index: coregrind/m_machine.c =================================================================== --- coregrind/m_machine.c.orig +++ coregrind/m_machine.c @@ -739,6 +739,7 @@ Bool VG_(machine_get_hwcaps)( void ) have_mmxext = True; va = VexArchX86; + vai.endness = VexEndnessLE; if (have_sse2 && have_sse1 && have_mmxext) { vai.hwcaps = VEX_HWCAPS_X86_MMXEXT; vai.hwcaps |= VEX_HWCAPS_X86_SSE1; @@ -857,14 +858,15 @@ Bool VG_(machine_get_hwcaps)( void ) have_avx2 = (ebx & (1<<5)) != 0; /* True => have AVX2 */ } - va = VexArchAMD64; - vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0) - | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0) - | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0) - | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0) - | (have_bmi ? VEX_HWCAPS_AMD64_BMI : 0) - | (have_avx2 ? VEX_HWCAPS_AMD64_AVX2 : 0) - | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0); + va = VexArchAMD64; + vai.endness = VexEndnessLE; + vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0) + | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0) + | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0) + | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0) + | (have_bmi ? VEX_HWCAPS_AMD64_BMI : 0) + | (have_avx2 ? VEX_HWCAPS_AMD64_AVX2 : 0) + | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0); VG_(machine_get_cache_info)(&vai); @@ -1013,6 +1015,7 @@ Bool VG_(machine_get_hwcaps)( void ) VG_(machine_ppc32_has_VMX) = have_V ? 1 : 0; va = VexArchPPC32; + vai.endness = VexEndnessBE; vai.hwcaps = 0; if (have_F) vai.hwcaps |= VEX_HWCAPS_PPC32_F; @@ -1151,6 +1154,9 @@ Bool VG_(machine_get_hwcaps)( void ) VG_(machine_ppc64_has_VMX) = have_V ? 1 : 0; va = VexArchPPC64; + // CARLL fixme: when the time comes, copy .endness setting code + // from the VGA_mips32 case + vai.endness = VexEndnessBE; vai.hwcaps = 0; if (have_V) vai.hwcaps |= VEX_HWCAPS_PPC64_V; @@ -1243,6 +1249,7 @@ Bool VG_(machine_get_hwcaps)( void ) r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); vg_assert(r == 0); va = VexArchS390X; + vai.endness = VexEndnessBE; vai.hwcaps = model; if (have_STFLE) vai.hwcaps |= VEX_HWCAPS_S390X_STFLE; @@ -1404,6 +1411,7 @@ Bool VG_(machine_get_hwcaps)( void ) VG_(machine_arm_archlevel) = archlevel; va = VexArchARM; + vai.endness = VexEndnessLE; vai.hwcaps = VEX_ARM_ARCHLEVEL(archlevel); if (have_VFP3) vai.hwcaps |= VEX_HWCAPS_ARM_VFP3; @@ -1419,6 +1427,7 @@ Bool VG_(machine_get_hwcaps)( void ) #elif defined(VGA_arm64) { va = VexArchARM64; + vai.endness = VexEndnessLE; /* So far there are no variants. */ vai.hwcaps = 0; @@ -1437,6 +1446,14 @@ Bool VG_(machine_get_hwcaps)( void ) vai.hwcaps = model; +# if defined(VKI_LITTLE_ENDIAN) + vai.endness = VexEndnessLE; +# elif defined(VKI_BIG_ENDIAN) + vai.endness = VexEndnessBE; +# else + vai.endness = VexEndness_INVALID; +# endif + /* Same instruction set detection algorithm as for ppc32/arm... */ vki_sigset_t saved_set, tmp_set; vki_sigaction_fromK_t saved_sigill_act; @@ -1506,11 +1523,19 @@ Bool VG_(machine_get_hwcaps)( void ) { va = VexArchMIPS64; UInt model = VG_(get_machine_model)(); - if (model== -1) + if (model == -1) return False; vai.hwcaps = model; +# if defined(VKI_LITTLE_ENDIAN) + vai.endness = VexEndnessLE; +# elif defined(VKI_BIG_ENDIAN) + vai.endness = VexEndnessBE; +# else + vai.endness = VexEndness_INVALID; +# endif + VG_(machine_get_cache_info)(&vai); return True; Index: coregrind/m_translate.c =================================================================== --- coregrind/m_translate.c.orig +++ coregrind/m_translate.c @@ -1641,8 +1641,7 @@ Bool VG_(translate) ( ThreadId tid, tmpbuf_used, tres.n_sc_extents > 0, tres.offs_profInc, - tres.n_guest_instrs, - vex_arch ); + tres.n_guest_instrs ); } else { vg_assert(tres.offs_profInc == -1); /* -1 == unset */ VG_(add_to_unredir_transtab)( &vge, ++++++ r14238.diff ++++++ ++++ 2098 lines (skipped) ++++++ r14239.diff ++++++ ++++ 4283 lines (skipped) ++++++ r14240.diff ++++++ ++++ 25958 lines (skipped) ++++++ r14246.diff ++++++ ------------------------------------------------------------------------ r14246 | carll | 2014-08-09 00:29:10 +0200 (Sa, 09. Aug 2014) | 10 Zeilen This commit is for Bugzilla 334834. A performance regression was found due to the -02 -m64 flags not being included when compiling the VEX PPC64 code. This commit fixes the Makefile to pass the needed flags when compiling VEX PPC64 code. ------------------------------------------------------------------------ Index: Makefile.all.am =================================================================== --- Makefile.all.am (Revision 14245) +++ Makefile.all.am (Revision 14246) @@ -163,9 +163,13 @@ AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@ AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g -AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@ -AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@ +AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g + +AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@ +AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@ AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \ ++++++ valgrind-r13948.diff ++++++ --- /var/tmp/diff_new_pack.56OktI/_old 2014-08-30 16:03:38.000000000 +0200 +++ /var/tmp/diff_new_pack.56OktI/_new 2014-08-30 16:03:38.000000000 +0200 @@ -3,12 +3,10 @@ Add test for MPX instructions and bnd prefix. Bug #333666. ------------------------------------------------------------------------ -Index: none/tests/amd64/mpx.stderr.exp -=================================================================== Index: none/tests/amd64/mpx.c =================================================================== ---- none/tests/amd64/mpx.c (revision 0) -+++ none/tests/amd64/mpx.c (revision 13948) +--- /dev/null ++++ none/tests/amd64/mpx.c @@ -0,0 +1,38 @@ +int +main (int argc, char **argv) @@ -48,20 +46,18 @@ + + return 0; +} -Index: none/tests/amd64/mpx.stdout.exp -=================================================================== Index: none/tests/amd64/mpx.vgtest =================================================================== ---- none/tests/amd64/mpx.vgtest (revision 0) -+++ none/tests/amd64/mpx.vgtest (revision 13948) +--- /dev/null ++++ none/tests/amd64/mpx.vgtest @@ -0,0 +1,3 @@ +prog: mpx +prereq: test -x mpx +vgopts: -q Index: none/tests/amd64/Makefile.am =================================================================== ---- none/tests/amd64/Makefile.am (revision 13947) -+++ none/tests/amd64/Makefile.am (revision 13948) +--- none/tests/amd64/Makefile.am.orig ++++ none/tests/amd64/Makefile.am @@ -56,6 +56,7 @@ EXTRA_DIST = \ loopnel.stderr.exp loopnel.stdout.exp loopnel.vgtest \ lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \ @@ -70,7 +66,7 @@ nan80and64.stderr.exp nan80and64.stdout.exp nan80and64.vgtest \ nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \ nibz_bennee_mmap.vgtest \ -@@ -133,6 +134,10 @@ endif +@@ -131,6 +132,10 @@ endif if BUILD_MOVBE_TESTS check_PROGRAMS += movbe endif @@ -83,9 +79,9 @@ if ! VGCONF_OS_IS_DARWIN Index: configure.ac =================================================================== ---- configure.ac (revision 13947) -+++ configure.ac (revision 13948) -@@ -2322,6 +2322,27 @@ AC_MSG_RESULT([no]) +--- configure.ac.orig ++++ configure.ac +@@ -2242,6 +2242,27 @@ AC_MSG_RESULT([no]) AM_CONDITIONAL(BUILD_FMA_TESTS, test x$ac_have_as_fma = xyes) -- To unsubscribe, e-mail: opensuse-commit+unsubscribe@opensuse.org For additional commands, e-mail: opensuse-commit+help@opensuse.org