https://bugzilla.suse.com/show_bug.cgi?id=1196465 https://bugzilla.suse.com/show_bug.cgi?id=1196465#c4 --- Comment #4 from Cyril Hrubis <chrubis@suse.com> --- Hi!

...

volatile int a, zero = 0, *zeroptr = &zero;

a = 1/(*zeroptr);

But technically it may even be a compiler bug, as far as I can tell the implementation cannot assume a value for a volatile variable in an any way.

None of that will help. ARM's SDIV and UDIV instructions simply do not trap:

Ah right, looking at the ARM specification it indeed does return 0. And for floating point there is a FPCR register where you can turn on/off if exceptions are generated in that case and it looks like it's off by default and has to be enabled. Also looks like QEMU does not even implement these registers. So I guess the best we can do is to directly raise() the SIGFPE on ARM. -- You are receiving this mail because: You are on the CC list for the bug.