http://bugzilla.suse.com/show_bug.cgi?id=1084812 http://bugzilla.suse.com/show_bug.cgi?id=1084812#c27 --- Comment #27 from Petr Tesařík <ptesarik@suse.com> --- All right, so this looks like ARM Cortex-A53 Erratum 843419, sequence 1:

1) An ADRP instruction, which writes to a register Rn. • This instruction must be located in memory at an address where the bottom 12 bits are equal to 0xFF8 or 0xFFC.

0x0000ffffb78d7ff8 <+24>: adrp x2, 0xffffb78f5000 Rn is x2

2) A load or store instruction: • This can be: • A single register load or store, of either integer or vector registers • Or an STP or STNP, of either integer or vector registers

0x0000ffffb78d7ffc <+28>: stp x4, x3, [x29, #104]

• Or an Advanced SIMD ST1 store instruction. • This must not write to Rn.

✓

[...] 3) There can optionally be one instruction after instruction 2.

Not here.

4) A load or store instruction from the "Load/store register (unsigned immediate)" encoding class, using Rn as the base address register.

0x0000ffffb78d8000 <+32>: ldr x3, [x2, #4040] -- You are receiving this mail because: You are on the CC list for the bug.