https://bugzilla.novell.com/show_bug.cgi?id=438986
User lurch@gmx.li added comment
https://bugzilla.novell.com/show_bug.cgi?id=438986#c3
Stefan Brüns changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEEDINFO |NEW
Info Provider|lurch@gmx.li |
--- Comment #3 from Stefan Brüns 2008-10-27 12:25:36 MDT ---
The following information is taken from
"Intel® 64 and IA-32 Architectures Software Developer's Manual
Volume 3A: System Programming Guide"
http://www.intel.com/products/processor/manuals/index.htm
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10.11.4.1 MTRR Precedences
[...]
- If two or more variable memory ranges match and one of the memory types
is UC, the UC memory type used.
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The memory range of the graphics (reg05) matches for the range defined by
reg03, leaving the memory range as uncached. The value in reg05 has no effect.
correct would be something like this:
..
reg0x: base=0xc0000000 (3072MB), size= 256MB: write-combining, count=1
reg0y: base=0xd0000000 (3328MB), size= 256MB: uncachable, count=1
reg0z: base=0xe0000000 (3584MB), size= 512MB: uncachable, count=1
Two registers are needed for the uncachable region due to size restriction of
ranges (2^n).
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