On Apr 22, 10 17:40:40 -0600, Ales Fiala wrote:
(II) RADEONHD(0): Minimum Pixel ClockPLL Frequency Output: 900000 (WW) RADEONHD(0): Higher minimum PLL output detected than the default: 648000 9000000. Please contact the authors ASAP.
(II) RADEONHD(0): Maximum Pixel ClockPLL Frequency Output: 1100000 So should the code be fixed to ignore the ATOMBIOS specified range and use the default range? With the default range there are no gaps in the pixel clock since it is wider. Or should the range be widened only a little to make all frequencies achievable? By my calculations the range of 732-1100 would be sufficient.
Can you try whether ignoring the AtomBIOS data completely helps? It
might well be that the BIOS is broken (and other drivers just don't rely
on the data).
AFAIK you are the first person who has a BIOS with a higher minimum PLL
freq :-)
If the lower values work for you I'd suggest to only use the AtomBIOS
values if they are lower than the default.
Matthias
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Matthias Hopf