On Mon, Sep 21, 2009 at 4:49 PM, Ales Fiala
Alex Deucher wrote:
On Mon, Sep 21, 2009 at 1:36 PM, Matthias Hopf
wrote: On Sep 18, 09 13:54:16 -0600, Ales Fiala wrote:
What is the meaning of the RV515_MC_STATUS:MC_IDLE bit?
The RV515/516 spec says it "Indicates that there are no pending or in-process requests in the MC."
There is code in RHDMCSetup() and RHDRestoreMC() that does the following: ASSERT((RHDRegRead(rhdPtr, D1VGA_CONTROL) & D1VGA_MODE_ENABLE) != D1VGA_MODE_ENABLE); ASSERT((RHDRegRead(rhdPtr, D2VGA_CONTROL) & D2VGA_MODE_ENABLE) != D2VGA_MODE_ENABLE); ASSERT((RHDRegRead(rhdPtr, D1CRTC_CONTROL) & 0x1) != 0x1); ASSERT((RHDRegRead(rhdPtr, D2CRTC_CONTROL) & 0x1) != 0x1); ASSERT(RHDMCIdle(rhdPtr, 1));
Hm. The code doesn't exist in the way you wrote it here. Either you are using pseudocode, or you're running on an old git version. If the later is the case, please try again with latest git.
If the former is the case, I assume you're talking about RV515MCWaitIdle().
I am getting infrequent failures in the last assertion, indicating that the MC is not idle. I verified that both the VGA anc CRTC controllers are indeed disabled, Yet the MC_IDLE bit is still wiggling. I wrote a little piece of code that reads it in a tight loop and indeed it comes on every 10-20 reads and then immediately goes off.
I assume you waited long enough so that there are definitely no acceleration commands left in the queue?
So if the CRTC and VGA controllers are not reading the memory, why is the MC not idle? Could it be that even if the screen is not being refreshed, the dynamic RAM still needs to be refreshed to keep it from losing its contents?
Sounds reasonable to me - but I guess only Alex can confirm or deny.
Likely the VGA engine is still doing something. Probably need to port something like:
http://cgit.freedesktop.org/xorg/driver/xf86-video-ati/commit/?id=52279251fa... to rhd. The MC should be idle when all memory clients (displays, 2D, 3D, overlays, etc. are off).
Alex
Thanks Alex. Dave Airlie also suggested checking the VGA_RENDER_CONTROL register, which seems to be what is included in the fix you mention. I have verified it and the VGA is disabled in this register also. I do not use 3D or overlays and they should be disabled, but I will double-check that too.
"2d" accel (EXA) also uses the 3D engine.
Could it be that the MC controller is performing the normal dynamic RAM refresh function? I seem to remember from long time ago that dynamic RAMS need to be refreshed regularly to keep them from losing their contents.
The MC idle bit refers to client blocks accessing video memory, so vram refresh doesn't apply here. You may want to check other status regs and see if any other blocks are active. Does the mc idle code in radeon (xf86-video-ati) also have trouble getting mc idle? If not, then you could compare reg states and see what might be different. Alex -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org