Hi, I've been fiddling with the power save features of the chip, in an effort to make my laptop a bit less of a space heater. Unfortunately I've been unable to get any results... :/ I've been using the included patch, which turns on any remaining power save feature on my board. Either I'm missing something or those features are doing a lot less than advertised (no measurable effect at all). Xorg.0.log output from this go: (II) RADEONHD(0): GENERAL_PWRMGT: 0x05 (II) RADEONHD(0): SCLK_PWRMGT_CNTL: 0x01 (II) RADEONHD(0): MCLK_PWRMGT_CNTL: 0x10015 (II) RADEONHD(0): DYN_PWRMGT_SCLK_CNTL: 0x101fac8f (II) RADEONHD(0): DYN_PWRMGT_SCLK_LENGTH: 0x44444444 (II) RADEONHD(0): DYN_SCLK_VOL_CNTL: 0x01 (II) RADEONHD(0): VIP_DYN_CNTL: 0xf3ff01a (II) RADEONHD(0): TCL_DYN_CNTL: 0x60a (II) RADEONHD(0): MC_GUI_DYN_CNTL: 0x12 (II) RADEONHD(0): MC_HOST_DYN_CNTL: 0x17 (II) RADEONHD(0): MC_RBS_DYN_CNTL: 0x16 Patch: diff --git a/src/rhd_driver.c b/src/rhd_driver.c index 90b9551..a719b66 100644 --- a/src/rhd_driver.c +++ b/src/rhd_driver.c @@ -736,6 +736,47 @@ RHDPreInit(ScrnInfoPtr pScrn, int flags) return ret; } +static void +rhdEnablePowerSave(RHDPtr rhdPtr) +{ + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, GENERAL_PWRMGT); + xf86DrvMsg(0, X_INFO, "GENERAL_PWRMGT: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, PLL_WR_EN | SCLK_PWRMGT_CNTL); + RHDRegWrite(rhdPtr, CLOCK_CNTL_DATA, RHDRegRead(rhdPtr, CLOCK_CNTL_DATA) | 0x1); + xf86DrvMsg(0, X_INFO, "SCLK_PWRMGT_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, MCLK_PWRMGT_CNTL); + xf86DrvMsg(0, X_INFO, "MCLK_PWRMGT_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, PLL_WR_EN | DYN_PWRMGT_SCLK_CNTL); + RHDRegWrite(rhdPtr, CLOCK_CNTL_DATA, RHDRegRead(rhdPtr, CLOCK_CNTL_DATA) | (1 << 20)); + xf86DrvMsg(0, X_INFO, "DYN_PWRMGT_SCLK_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, PLL_WR_EN | DYN_PWRMGT_SCLK_LENGTH); + RHDRegWrite(rhdPtr, CLOCK_CNTL_DATA, 0x44444444); + xf86DrvMsg(0, X_INFO, "DYN_PWRMGT_SCLK_LENGTH: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, PLL_WR_EN | DYN_SCLK_VOL_CNTL); + RHDRegWrite(rhdPtr, CLOCK_CNTL_DATA, RHDRegRead(rhdPtr, CLOCK_CNTL_DATA) | 0x1); + xf86DrvMsg(0, X_INFO, "DYN_SCLK_VOL_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, VIP_DYN_CNTL); + xf86DrvMsg(0, X_INFO, "VIP_DYN_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, TCL_DYN_CNTL); + xf86DrvMsg(0, X_INFO, "TCL_DYN_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, MC_GUI_DYN_CNTL); + xf86DrvMsg(0, X_INFO, "MC_GUI_DYN_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, MC_HOST_DYN_CNTL); + xf86DrvMsg(0, X_INFO, "MC_HOST_DYN_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); + + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, MC_RBS_DYN_CNTL); + xf86DrvMsg(0, X_INFO, "MC_RBS_DYN_CNTL: 0x%02x\n", RHDRegRead(rhdPtr, CLOCK_CNTL_DATA)); +} + /* Mandatory */ static Bool RHDScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) @@ -767,6 +808,9 @@ RHDScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) /* save previous mode */ rhdSave(rhdPtr); + /* enable dynamice power save */ + rhdEnablePowerSave(rhdPtr); + /* now init the new mode */ rhdModeInit(pScrn, pScrn->currentMode); diff --git a/src/rhd_regs.h b/src/rhd_regs.h index 6c5d7c1..4817a1d 100644 --- a/src/rhd_regs.h +++ b/src/rhd_regs.h @@ -271,7 +271,18 @@ enum _r5xxRegs { }; enum _r5xxSPLLRegs { - SPLL_FUNC_CNTL = 0x0 /* (RW) */ + SPLL_FUNC_CNTL = 0x0, /* (RW) */ + GENERAL_PWRMGT = 0x8, /* (RW) */ + SCLK_PWRMGT_CNTL = 0x9, /* (RW) */ + MCLK_PWRMGT_CNTL = 0xA, /* (RW) */ + DYN_PWRMGT_SCLK_CNTL = 0xB, /* (RW) */ + DYN_PWRMGT_SCLK_LENGTH = 0xC, /* (RW) */ + DYN_SCLK_VOL_CNTL = 0xE, /* (RW) */ + VIP_DYN_CNTL = 0x14, /* (RW) */ + TCL_DYN_CNTL = 0x1A, /* (RW) */ + MC_GUI_DYN_CNTL = 0x1D, /* (RW) */ + MC_HOST_DYN_CNTL = 0x1E, /* (RW) */ + MC_RBS_DYN_CNTL = 0x26, /* (RW) */ }; enum _r6xxRegs { -- -- Pierre Ossman Linux kernel, MMC maintainer http://www.kernel.org PulseAudio, core developer http://pulseaudio.org rdesktop, core developer http://www.rdesktop.org -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org