diff --git a/src/r600_state.h b/src/r600_state.h
index 6ee59f9..be70c4d 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -169,11 +169,70 @@ typedef struct {
     uint32_t num_indices;
 } draw_config_t;
 
-inline void e32(drmBufPtr ib, uint32_t dword);
-inline void efloat(drmBufPtr ib, float f);
-inline void pack3(drmBufPtr ib, int cmd, unsigned num);
-inline void pack0 (drmBufPtr ib, uint32_t reg, int num);
-inline void ereg (drmBufPtr ib, uint32_t reg, uint32_t val);
+/* Emit uint32_t */
+static inline void e32(drmBufPtr ib, uint32_t dword)
+{
+    uint32_t *ib_head = (pointer)(char*)ib->address;
+
+    ib_head[ib->used>>2] = dword;
+    ib->used += 4;
+}
+
+static inline void efloat(drmBufPtr ib, float f)
+{
+    union {
+        float f;
+        uint32_t d;
+    } a;
+    a.f=f;
+    e32(ib, a.d);
+}
+
+static inline void pack3(drmBufPtr ib, int cmd, unsigned num)
+{
+    e32 (ib, RADEON_CP_PACKET3 | (cmd << 8) | (((num-1) & 0x3fff) << 16));
+}
+
+/* write num registers, start at reg */
+/* If register falls in a special area, special commands are issued */
+static inline void pack0 (drmBufPtr ib, uint32_t reg, int num)
+{
+    if (reg >= SET_CONFIG_REG_offset && reg < SET_CONFIG_REG_end) {
+        pack3 (ib, IT_SET_CONFIG_REG, num+1);
+        e32 (ib, (reg-SET_CONFIG_REG_offset) >> 2);
+    } else if (reg >= SET_CONTEXT_REG_offset && reg < SET_CONTEXT_REG_end) {
+        pack3 (ib, IT_SET_CONTEXT_REG, num+1);
+        e32 (ib, (reg-0x28000) >> 2);
+    } else if (reg >= SET_ALU_CONST_offset && reg < SET_ALU_CONST_end) {
+        pack3 (ib, IT_SET_ALU_CONST, num+1);
+        e32 (ib, (reg-SET_ALU_CONST_offset) >> 2);
+    } else if (reg >= SET_RESOURCE_offset && reg < SET_RESOURCE_end) {
+        pack3 (ib, IT_SET_RESOURCE, num+1);
+        e32 (ib, (reg-SET_RESOURCE_offset) >> 2);
+    } else if (reg >= SET_SAMPLER_offset && reg < SET_SAMPLER_end) {
+        pack3 (ib, IT_SET_SAMPLER, num+1);
+        e32 (ib, (reg-SET_SAMPLER_offset) >> 2);
+    } else if (reg >= SET_CTL_CONST_offset && reg < SET_CTL_CONST_end) {
+        pack3 (ib, IT_SET_CTL_CONST, num+1);
+        e32 (ib, (reg-SET_CTL_CONST_offset) >> 2);
+    } else if (reg >= SET_LOOP_CONST_offset && reg < SET_LOOP_CONST_end) {
+        pack3 (ib, IT_SET_LOOP_CONST, num+1);
+        e32 (ib, (reg-SET_LOOP_CONST_offset) >> 2);
+    } else if (reg >= SET_BOOL_CONST_offset && reg < SET_BOOL_CONST_end) {
+        pack3 (ib, IT_SET_BOOL_CONST, num+1);
+        e32 (ib, (reg-SET_BOOL_CONST_offset) >> 2);
+    } else {
+        e32 (ib, CP_PACKET0 (reg, num-1));
+    }
+}
+
+/* write a single register */
+static inline void ereg (drmBufPtr ib, uint32_t reg, uint32_t val)
+{
+    pack0 (ib, reg, 1);
+    e32   (ib, val);
+}
+
 void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib);
 uint64_t
 upload (ScrnInfoPtr pScrn, void *shader, int size, int offset);
@@ -213,8 +272,10 @@ void
 set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
 void
 set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib);
+#if 0
 void
 draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices);
+#endif
 void
 draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
 
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 8ddf608..fc289ee 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -54,70 +54,6 @@
 
 #define RADEON_TIMEOUT    2000000
 
-/* Emit uint32_t */
-inline void e32(drmBufPtr ib, uint32_t dword)
-{
-    uint32_t *ib_head = (pointer)(char*)ib->address;
-
-    ib_head[ib->used>>2] = dword;
-    ib->used += 4;
-}
-
-inline void efloat(drmBufPtr ib, float f)
-{
-    union {
-	float f;
-	uint32_t d;
-    } a;
-    a.f=f;
-    e32(ib, a.d);
-}
-
-inline void pack3(drmBufPtr ib, int cmd, unsigned num)
-{
-    e32 (ib, RADEON_CP_PACKET3 | (cmd << 8) | (((num-1) & 0x3fff) << 16));
-}
-
-/* write num registers, start at reg */
-/* If register falls in a special area, special commands are issued */
-inline void pack0 (drmBufPtr ib, uint32_t reg, int num)
-{
-    if (reg >= SET_CONFIG_REG_offset && reg < SET_CONFIG_REG_end) {
-	pack3 (ib, IT_SET_CONFIG_REG, num+1);
-	e32 (ib, (reg-SET_CONFIG_REG_offset) >> 2);
-    } else if (reg >= SET_CONTEXT_REG_offset && reg < SET_CONTEXT_REG_end) {
-	pack3 (ib, IT_SET_CONTEXT_REG, num+1);
-	e32 (ib, (reg-0x28000) >> 2);
-    } else if (reg >= SET_ALU_CONST_offset && reg < SET_ALU_CONST_end) {
-	pack3 (ib, IT_SET_ALU_CONST, num+1);
-	e32 (ib, (reg-SET_ALU_CONST_offset) >> 2);
-    } else if (reg >= SET_RESOURCE_offset && reg < SET_RESOURCE_end) {
-	pack3 (ib, IT_SET_RESOURCE, num+1);
-	e32 (ib, (reg-SET_RESOURCE_offset) >> 2);
-    } else if (reg >= SET_SAMPLER_offset && reg < SET_SAMPLER_end) {
-	pack3 (ib, IT_SET_SAMPLER, num+1);
-	e32 (ib, (reg-SET_SAMPLER_offset) >> 2);
-    } else if (reg >= SET_CTL_CONST_offset && reg < SET_CTL_CONST_end) {
-	pack3 (ib, IT_SET_CTL_CONST, num+1);
-	e32 (ib, (reg-SET_CTL_CONST_offset) >> 2);
-    } else if (reg >= SET_LOOP_CONST_offset && reg < SET_LOOP_CONST_end) {
-	pack3 (ib, IT_SET_LOOP_CONST, num+1);
-	e32 (ib, (reg-SET_LOOP_CONST_offset) >> 2);
-    } else if (reg >= SET_BOOL_CONST_offset && reg < SET_BOOL_CONST_end) {
-	pack3 (ib, IT_SET_BOOL_CONST, num+1);
-	e32 (ib, (reg-SET_BOOL_CONST_offset) >> 2);
-    } else {
-	e32 (ib, CP_PACKET0 (reg, num-1));
-    }
-}
-
-/* write a single register */
-inline void ereg (drmBufPtr ib, uint32_t reg, uint32_t val)
-{
-    pack0 (ib, reg, 1);
-    e32   (ib, val);
-}
-
 /* Flush the indirect buffer to the kernel for submission to the card */
 void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib)
 {
