What | Removed | Added |
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CC | bpoirier@suse.com, tiwai@suse.com |
Hm, this looks like happening at do_div() in e1000e_cyclecounter_read() static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc) { ...... if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) { u64 incvalue, time_delta, rem, temp; ...... incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { /* latch SYSTIMH on read of SYSTIML */ systim_next = (cycle_t)er32(SYSTIML); systim_next |= (cycle_t)er32(SYSTIMH) << 32; time_delta = systim_next - systim; temp = time_delta; rem = do_div(temp, incvalue); That is, the bit value read from TIMINCA register is zero.