Mailinglist Archive: radeonhd (408 mails)

[Egbert Eich <eich@xxxxxxx>]

Dariem Pérez Herrera writes:
> --- rhd_regs-old.h   2009-06-26 00:09:40.000000000 -0400
> +++ rhd_regs.h       2009-06-26 00:11:36.000000000 -0400
> @@ -32,9 +32,14 @@
>      MC_IND_INDEX      =       0x70, /* (RW) */
>      MC_IND_DATA           =       0x74, /* (RW) */
>      CONFIG_CNTL               =       0xE0,
> +    /* RS600: taken from xf86-video-ati*/
> +    RS60_MC_NB_MC_INDEX       =       0x70,
> +    RS60_MC_NB_MC_DATA        =       0x74,
>      /* RS690 ?? */
> +    /*
>      RS60_MC_NB_MC_INDEX               =       0x78,
>      RS60_MC_NB_MC_DATA                =       0x7C,
> +    */
>      RS69_MC_INDEX             =       0xE8,
>      RS69_MC_DATA              =       0xEC,
>      R5XX_CONFIG_MEMSIZE            = 0x00F8,

This change sets the RS600 values to exactly the same values as for 
R5XX. The difference between R5XX chips and RS600 is that the latter
ones are IGP chipsets.
I've taken the RS60_MC_NB_MC_INDEX and RS60_MC_NB_MC_DATA straight
out of a register listing I've received from ATI. Some of those 
have proven to be incorrect - especially regarding MC registers.

I've never had the chance to try out RS600 as I've never had a system,
thus I had to fully depend on the data books.
It's also possible that the R5XX registers always return 1 in all
bits thus trivially appear to have the idle bit set.
Maybe you want to try this with some ErrorFs.


Cheers,
        Egbert.
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