Mailinglist Archive: radeonhd (408 mails)
| < Previous | Next > |
Re: [radeonhd] More powermanagement stuff to try out
- From: Alex Deucher <alexdeucher@xxxxxxxxx>
- Date: Tue, 9 Jun 2009 10:56:34 -0400
- Message-id: <a728f9f90906090756ma656ab5q5fba6bba361472c8@xxxxxxxxxxxxxx>
2009/6/9 Rafał Miłecki <zajec5@xxxxxxxxx>:
This table is empty on r6xx hardware. The hw is different on r6xx and
newer asics.
The GPU will turn off the clock to various blocks on the chip when
they are idle to save power. When they are requested, they are
powered back up. You can pick at the block level which blocks
participate or not.
It enables automatic lower clocks for things like PCI D states. I'm
not sure it makes much difference under normal circumstances.
I'm not sure what the former is used for. I suspect it's used when
changing power states. The latter two are used for memory setup and
are called by other tables like SetMemoryClock or AsicInit.
Alex
--
To unsubscribe, e-mail: radeonhd+unsubscribe@xxxxxxxxxxxx
For additional commands, e-mail: radeonhd+help@xxxxxxxxxxxx
2009/6/5 Matthias Hopf <mhopf@xxxxxxx>:
After some discussion with AMD we found that there is a chance that with
only some additional AtomBIOS calls we might be able to get to the same
power levels as fglrx.
With the following patch these are included, but only called if Option
"ForceLowPowerMode" is active. I'd like to have this tested before
I actually commit this. I tested it here and it *seems* to work -
I don't have a power meter at hand for validation at the moment.
What we're still missing are
- PCIe lane changes
- Memory clock changes
- Dynamic clock changes
- Core voltage changes
For all of them enough documentation is available already. So if *this*
patch actually helps reducing power consumption, we probably have enough
information for fully implemented power management.
What we're still missing information for are
- Which clock/voltage settings are stable
- What is the minimum core / memory clock
Maybe we'll find something by looking at the V4 version of the PowerPlay
AtomBIOS table (of which we currently don't know the details yet). Maybe
it helps smoking something while staring at the hexdumps =->>>
I've some newbie questions.
First of all, why do we use DynamicClockGating only for
(rhdPtr->ChipSet < RHD_R600)? Is this enabled by default on everything
newer than R600?
This table is empty on r6xx hardware. The hw is different on r6xx and
newer asics.
How does DynamicClockGating work? Does GPU knows itself all (unused)
hardware blocks than he can stop clocking?
The GPU will turn off the clock to various blocks on the chip when
they are idle to save power. When they are requested, they are
powered back up. You can pick at the block level which blocks
participate or not.
What actually is EnableASIC_StaticPwrMgt? Is this something we need to
enable before using DynamicClockGating? If so, what other AtomBIOS
commands depend on EnableASIC_StaticPwrMgt?
It enables automatic lower clocks for things like PCI D states. I'm
not sure it makes much difference under normal circumstances.
Could someone explain shortly other AtomBIOS commands like:
ASIC_StaticPwrMgtStatusChange, DynamicMemorySettings, MemoryTraining
I'm not sure what the former is used for. I suspect it's used when
changing power states. The latter two are used for memory setup and
are called by other tables like SetMemoryClock or AsicInit.
Alex
--
To unsubscribe, e-mail: radeonhd+unsubscribe@xxxxxxxxxxxx
For additional commands, e-mail: radeonhd+help@xxxxxxxxxxxx
| < Previous | Next > |