Am Sonntag, den 07.06.2009, 20:42 +0200 schrieb Rafał Miłecki:
am I right? Can someone check this with me, please? Do we really use RV620PLL* for listed chipsets? Mhm, yes that's seems to be what the current implementation is doing.
For full explaination, please read http://bugs.freedesktop.org/show_bug.cgi?id=18016
Short explaination:
libv: ah, rv620/635. libv: this is where the beautifully separated hw blocks got mucked together on the pll side.
rv620/635 is tricky about PLL engines. These aren't 100% separated and it seems we can't really disable any on them at any time. It seems for example we have to keep PLL1 running if we use PLL2 for driving some output. Wow, this is a really long bugreport. Ok i got it, the problem seems to be a little bit more complicated than i thought, but i think the real solution would be to move the whole handling of RV620_EXT[12]_DIFF_POST_DIV_CNTL from rhd_dig.c to rhd_pll.c.
And bye the way i think i found a bug in rhd_dig.c:EncoderRestore and rhd_dig.c:EncoderSave, RV620_EXT[12]_DIFF_POST_DIV_CNTL is added to the DIG offset, while every other read/write goes to the addresses directly. Bye, Christian. -- To unsubscribe, e-mail: radeonhd+unsubscribe@opensuse.org For additional commands, e-mail: radeonhd+help@opensuse.org