Mailinglist Archive: radeonhd (408 mails)
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[radeonhd] [Bug 18016] Disabling PANEL disables DVI-D_1
- From: bugzilla-daemon@xxxxxxxxxxxxxxx
- Date: Sat, 6 Jun 2009 11:50:33 -0700 (PDT)
- Message-id: <20090606185033.580B0130016@xxxxxxxxxxxxxxxxxxxxxxxx>
http://bugs.freedesktop.org/show_bug.cgi?id=18016
--- Comment #39 from Rafał Miłecki <zajec5@xxxxxxxxx> 2009-06-06 11:50:31 PST
---
Using attached patch I traced AtomBIOS registers operations for disabling PLL1:
[AtomBIOS]: CailWriteATIRegister(6080,1400310)
[AtomBIOS]: CailWriteATIRegister(538,1)
[AtomBIOS]: CailWriteATIRegister(384,0)
[AtomBIOS]: CailWriteATIRegister(38c,0)
[AtomBIOS]: CailWriteATIRegister(394,0)
[AtomBIOS]: CailWriteATIRegister(438,0)
[AtomBIOS]: CailWriteATIRegister(468,202)
[AtomBIOS]: CailWriteATIRegister(470,200b)
[AtomBIOS]: CailWriteATIRegister(450,6c310001)
[AtomBIOS]: CailWriteATIRegister(450,6c012001)
Disabling PLL1 using SetPixelClock AtomBIOS command includes disabling CRTC1.
That explains touching 6080 register.
Next I found code in disassembled AtomBIOS responsible for these operations:
/* 0538 == DCCG_DISP_CLK_SRCSEL */
→ 00bc: 01254e0101 MOVE reg[0538] [...X] <- 01
00c1: 43c900 JUMP 00c9
00c4: 01254e0103 MOVE reg[0538] [...X] <- 03
→ 00c9: 5420e100 CLEAR reg[0384] [...X]
→ 00cd: 5420e300 CLEAR reg[038c] [...X]
→ 00d1: 5420e500 CLEAR reg[0394] [...X]
00d5: 3d250200 COMP param[02] [...X] <- 00
00d9: 49e300 JUMP_NotEqual 00e3
/* 0438 == EXT1_PPLL_POST_DIV_SRC */
→ 00dc: 54200e01 CLEAR reg[0438] [...X]
00e0: 43ea00 JUMP 00ea
00e3: 54201001 CLEAR reg[0440] [...X]
00e7: 3a0100 SET_REG_BLOCK 0001
/* 0468 == P1PLL_DISP_CLK_CNTL */
→ 00ea: 01651a0102 MOVE reg[0468] [..X.] <- 02
/* 0470 == EXT1_SYM_PPLL_POST_DIV */
→ 00ef: 07651c01fe AND reg[0470] [..X.] <- fe
/* 0450 == P1PLL_CNTL */
→ 00f4: 0d25140101 OR reg[0450] [...X] <- 01
→ 00f9: 5102 DELAY_MicroSec 02
00fb: 3d0d000000 COMP param[00] [..XX] <- 0000
0100: 491001 JUMP_NotEqual 0110
0103: 4a65080101 TEST reg[0420] [..X.] <- 01
0108: 491001 JUMP_NotEqual 0110
010b: 0d25140102 OR reg[0450] [...X] <- 02
→ 0110: 51c8 DELAY_MicroSec c8
/* 0450 == P1PLL_CNTL */
→ 0112: 0d65140120 OR reg[0450] [..X.] <- 20
--
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--- Comment #39 from Rafał Miłecki <zajec5@xxxxxxxxx> 2009-06-06 11:50:31 PST
---
Using attached patch I traced AtomBIOS registers operations for disabling PLL1:
[AtomBIOS]: CailWriteATIRegister(6080,1400310)
[AtomBIOS]: CailWriteATIRegister(538,1)
[AtomBIOS]: CailWriteATIRegister(384,0)
[AtomBIOS]: CailWriteATIRegister(38c,0)
[AtomBIOS]: CailWriteATIRegister(394,0)
[AtomBIOS]: CailWriteATIRegister(438,0)
[AtomBIOS]: CailWriteATIRegister(468,202)
[AtomBIOS]: CailWriteATIRegister(470,200b)
[AtomBIOS]: CailWriteATIRegister(450,6c310001)
[AtomBIOS]: CailWriteATIRegister(450,6c012001)
Disabling PLL1 using SetPixelClock AtomBIOS command includes disabling CRTC1.
That explains touching 6080 register.
Next I found code in disassembled AtomBIOS responsible for these operations:
/* 0538 == DCCG_DISP_CLK_SRCSEL */
→ 00bc: 01254e0101 MOVE reg[0538] [...X] <- 01
00c1: 43c900 JUMP 00c9
00c4: 01254e0103 MOVE reg[0538] [...X] <- 03
→ 00c9: 5420e100 CLEAR reg[0384] [...X]
→ 00cd: 5420e300 CLEAR reg[038c] [...X]
→ 00d1: 5420e500 CLEAR reg[0394] [...X]
00d5: 3d250200 COMP param[02] [...X] <- 00
00d9: 49e300 JUMP_NotEqual 00e3
/* 0438 == EXT1_PPLL_POST_DIV_SRC */
→ 00dc: 54200e01 CLEAR reg[0438] [...X]
00e0: 43ea00 JUMP 00ea
00e3: 54201001 CLEAR reg[0440] [...X]
00e7: 3a0100 SET_REG_BLOCK 0001
/* 0468 == P1PLL_DISP_CLK_CNTL */
→ 00ea: 01651a0102 MOVE reg[0468] [..X.] <- 02
/* 0470 == EXT1_SYM_PPLL_POST_DIV */
→ 00ef: 07651c01fe AND reg[0470] [..X.] <- fe
/* 0450 == P1PLL_CNTL */
→ 00f4: 0d25140101 OR reg[0450] [...X] <- 01
→ 00f9: 5102 DELAY_MicroSec 02
00fb: 3d0d000000 COMP param[00] [..XX] <- 0000
0100: 491001 JUMP_NotEqual 0110
0103: 4a65080101 TEST reg[0420] [..X.] <- 01
0108: 491001 JUMP_NotEqual 0110
010b: 0d25140102 OR reg[0450] [...X] <- 02
→ 0110: 51c8 DELAY_MicroSec c8
/* 0450 == P1PLL_CNTL */
→ 0112: 0d65140120 OR reg[0450] [..X.] <- 20
--
Configure bugmail: http://bugs.freedesktop.org/userprefs.cgi?tab=email
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