Mailinglist Archive: radeonhd (424 mails)

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Re: [radeonhd] Dynamic clock setting
  • From: Alex Deucher <alexdeucher@xxxxxxxxx>
  • Date: Wed, 27 May 2009 13:48:33 -0400
  • Message-id: <a728f9f90905271048u22b0459dw87672992fb0d47e5@xxxxxxxxxxxxxx>
On Wed, May 27, 2009 at 12:40 PM, Yang Zhao <yang@xxxxxxxxxx> wrote:
2009/5/27 Alex Deucher <alexdeucher@xxxxxxxxx>:
On Tue, May 26, 2009 at 9:32 PM, Yang Zhao <yang@xxxxxxxxxx> wrote:
Hi all,

I've been looking through disassembled AtomBIOS code for my RV770, and
noticed that SetEngineClock seems to be doing its own wait-for-value
busy loop on certain undocumented registers. In fact, it appears that,
at least on r7xx, there is no explicit idling requiring before calling
AtomBIOS' SetMemoryClock and SetEngineClock.


It's waiting for the engine PLL to lock. It's still a good idea to
wait for the engine to be idle when changing the clock to avoid
possible drawing problems or lockups.

Yup. Still slowly working on that idle code refactoring...

Incidentally, what does SRBM and GRBM stand for?

System Register Backbone Manager
Graphics Register Backbone Manager



#define R600_CG_SPLL_STATUS               0x60c
#           define R600_SPLL_CHG_STATUS  (1 << 1)

I've been looking for a name for those registers, but it's apparently
not in rhd's headers. Looks like radeon's using it for something rhd
doesn't do.

It's used in radeon for reading disabled roms on r7xx chips. See radeon_bios.c.

Alex
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