Mailinglist Archive: radeonhd (312 mails)

[Matthias Hopf <mhopf@xxxxxxx>]

On Mar 26, 09 09:45:46 +1300, Michael Cree wrote:
> Memory barriers, at least of some sort, are defined to be non-empty in 
> compiler.h for the following architectures: alpha, ia64, amd64, mips and 
> powerpc.

I just checked the linux kernel headers (mb macro):

It's a NOP on cris, m32r, m68k, mn10300, parisc, and xtensa.
It's actual code on frv, mips, and x86.

I stand corrected, though I'm puzzled which x86 processors need barriers
(the comments in the code states "Some non-Intel clones support out of
order store. wmb() ceases to be a * nop for these."). I don't think
Athlons do that.

BTW - what architecture is frv? How is powerpc, alpha, and ia64 called
in kernel land? Do you happen to know?

CU

Matthias

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