Mailinglist Archive: radeonhd (312 mails)

[Matthias Hopf <mhopf@xxxxxxx>]

On Mar 26, 09 09:45:46 +1300, Michael Cree wrote:
> > > > > If the radeonhd developers indicate that they are prepared to merge
> > > > > such patches then I am happy to spend more time on writing a new patch
> > > > > that redefines the macro definitions in rhd.h.
> > No probs. I think there aren't too many Alpha users out there besides
> > you ;-)
>
> I suspect you have missed the point.  It is not relevant to Alpha users 
> only - it is relevant to users of a number of different architectures.
>
> Memory barriers, at least of some sort, are defined to be non-empty in 
> compiler.h for the following architectures: alpha, ia64, amd64, mips and 
> powerpc.
>
> Note the presence of amd64 in that list!  With the growing number of people 
> using amd64 I would want to know exactly what the issues are with the amd64 
> memory barrier before writing code that uses direct memory access only to 
> I/O ports.

x86_64 is a i386 architekture, and that defines that memory accesses may
not be reordered AFAIR. I only know of alpha that actually does
reordering in hardware, and compiler reordering will not be done due to
the volatile accesses.

Nevertheless it would be interesting to verify whether any bugs are gone
as soon as barriers are done correctly. I doubt there will be any, but
you never know.

Matthias

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Matthias Hopf <mhopf@xxxxxxx>      __        __   __
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