Mailinglist Archive: radeonhd (307 mails)

< Previous Next >
Re: [radeonhd] [PATCH] r6xx/r7xx Q&D implementation of wait_vblank
  • From: Alex Deucher <alexdeucher@xxxxxxxxx>
  • Date: Tue, 10 Feb 2009 17:32:27 -0500
  • Message-id: <a728f9f90902101432r20727ef7q6051a455ed0ddadb@xxxxxxxxxxxxxx>
On Tue, Feb 10, 2009 at 4:43 PM, Christian König
<deathsimple@xxxxxxxxxxx> wrote:
Am Dienstag, den 10.02.2009, 19:01 +0100 schrieb Matthias Hopf:
Comparing for a particular line is definitely better, because you can
wait for the first line after the visible area, which might be earlier
than vblank due to overscan.
Ok, implemented it as you suggested. Patch is attached.

You can push a type-3 packet that writes the current GPU 64bit counter
into some memory address as soon as the pipeline is finished (and this
actually even doesn't stall the engine).
Is there some documentation of the type-3 packets available for r6xx?
I've found the docs for r5xx, but can't find any thing mentioned about
it in the r6xx isa and register documentations. Am i missing something?


The opcodes are in the headers we released, but the descriptions are
part of the soon to be released programming guide.

What i had in mind was reading out the horizontal and vertical count
register before draw_auto and after wait_3d_idle, so i could calc how
much time a specific operation needs in terms of pixel clock and/or
vertical scanout. For this i need copy operation from a register to a
memory address, but i don't know if that is possible with an cp opcode.

You're still waiting more than you need to. You should set the start
and stop vlines and just wait for the scanout be be outside of the
that range.

Alex
--
To unsubscribe, e-mail: radeonhd+unsubscribe@xxxxxxxxxxxx
For additional commands, e-mail: radeonhd+help@xxxxxxxxxxxx

< Previous Next >
Follow Ups