Mailinglist Archive: radeonhd (265 mails)
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Re: [radeonhd] Re: Initial Radeon R6xx/R7xx acceleration support pushed
- From: Christian König <deathsimple@xxxxxxxxxxx>
- Date: Fri, 02 Jan 2009 01:59:39 +0100
- Message-id: <1230857979.7772.41.camel@zweiundvierzig>
Happy new year,
Am Dienstag, den 30.12.2008, 10:41 -0500 schrieb Alex Deucher:
I already figured this out myself, so i started hacking the drm code a
little bit: I adjusted all calculations with the pcigart scatter-gather
address within r600_cp.c to match the one in radeon_cp.c, this fixed the
kernel oops and even allows xserver with xvideo support to start.
Playing some MPEG with mplayer displays something which looks like
random pixel data, so i think the only thing missing is programming the
agpgart addresses into the hardware, but here my knowledge really stops.
A patch is attached, is AGP support something witch is showing up soon?
I can't wait to crash the xserver while watch videos with xv, and start
hacking the hardware directly.
Bye, Christian.
# Not currently on any branch.
# Changes to be committed:
# (use "git reset HEAD <file>..." to unstage)
#
# modified: shared-core/r600_cp.c
# modified: shared-core/radeon_cp.c
# modified: shared-core/radeon_drv.h
#
# Untracked files:
# (use "git add <file>..." to include in what will be committed)
#
# drm-agp.patch
# linux-core/Module.markers
# linux-core/modules.order
diff --git a/shared-core/r600_cp.c b/shared-core/r600_cp.c
index 6436ffc..a1320b9 100644
--- a/shared-core/r600_cp.c
+++ b/shared-core/r600_cp.c
@@ -470,10 +470,9 @@ static int r600_page_table_init(struct drm_device *dev)
memset(pci_gart, 0, max_pages * sizeof(u64));
for (i = 0; i < pages; i++) {
- entry->busaddr[i] = pci_map_single(dev->pdev,
- page_address(entry->
- pagelist[i]),
- PAGE_SIZE, PCI_DMA_TODEVICE);
+ entry->busaddr[i] = pci_map_single(dev->pdev,
+ page_address(entry->pagelist[i]),
+ PAGE_SIZE, PCI_DMA_TODEVICE);
if (entry->busaddr[i] == 0) {
DRM_ERROR("unable to map PCIGART pages!\n");
r600_page_table_cleanup(dev, gart_info);
@@ -2003,6 +2002,16 @@ static void r600_cp_init_ring_buffer(struct drm_device *
dev,
SET_RING_HEAD(dev_priv, 0);
dev_priv->ring.tail = 0;
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
+ (dev_priv->ring_rptr->offset
+ - dev->agp->base
+ + dev_priv->gart_vm_start)
+ >> 8);
+ RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 0);
+ } else
+#endif
{
struct drm_sg_mem *entry = dev->sg;
unsigned long tmp_ofs, page_ofs;
@@ -2029,9 +2038,23 @@ static void r600_cp_init_ring_buffer(struct drm_device *
dev,
dev_priv->ring.size_l2qw);
#endif
- ring_start = (dev_priv->cp_ring->offset
- - (unsigned long)dev->sg->virtual
- + dev_priv->gart_vm_start);
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ radeon_write_agp_base(dev_priv, dev->agp->base);
+
+ radeon_write_agp_location(dev_priv,
+ (((dev_priv->gart_vm_start - 1 +
+ dev_priv->gart_size) & 0xffff0000) |
+ (dev_priv->gart_vm_start >> 16)));
+
+ ring_start = (dev_priv->cp_ring->offset
+ - dev->agp->base
+ + dev_priv->gart_vm_start);
+ } else
+#endif
+ ring_start = (dev_priv->cp_ring->offset
+ - (unsigned long)dev->sg->virtual
+ + dev_priv->gart_vm_start);
RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
@@ -2279,6 +2302,18 @@ int r600_do_init_cp(struct drm_device * dev,
drm_radeon_init_t * init)
* location in the card and on the bus, though we have to
* align it down.
*/
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ base = dev->agp->base;
+ /* Check if valid */
+ if ((base + dev_priv->gart_size - 1) >=
dev_priv->fb_location &&
+ base < (dev_priv->fb_location + dev_priv->fb_size
- 1)) {
+ DRM_INFO("Can't use AGP base @0x%08lx, won't
fit\n",
+ dev->agp->base);
+ base = 0;
+ }
+ }
+#endif
/* If not or if AGP is at 0 (Macs), try to put it elsewhere */
if (base == 0) {
base = dev_priv->fb_location + dev_priv->fb_size;
@@ -2293,9 +2328,16 @@ int r600_do_init_cp(struct drm_device * dev,
drm_radeon_init_t * init)
base, dev_priv->gart_vm_start);
}
- dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
- - (unsigned long)dev->sg->virtual
- + dev_priv->gart_vm_start);
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP)
+ dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
+ - dev->agp->base
+ + dev_priv->gart_vm_start);
+ else
+#endif
+ dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
+ - (unsigned
long)dev->sg->virtual
+ + dev_priv->gart_vm_start);
DRM_DEBUG("fb 0x%08x size %d\n", dev_priv->fb_location,
dev_priv->fb_size);
DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
@@ -2319,28 +2361,38 @@ int r600_do_init_cp(struct drm_device * dev,
drm_radeon_init_t * init)
dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
- dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
- /* if we have an offset set from userspace */
- if (!dev_priv->pcigart_offset_set)
- DRM_ERROR("Need gart offset from userspace\n");
-
- dev_priv->gart_info.bus_addr =
- dev_priv->pcigart_offset + dev_priv->fb_location;
- dev_priv->gart_info.mapping.offset =
- dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
- dev_priv->gart_info.mapping.size =
- dev_priv->gart_info.table_size;
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ /* Turn off PCI GART */
+ //radeon_set_pcigart(dev_priv, 0);
+ } else
+#endif
+ {
+ dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
+
+ /* if we have an offset set from userspace */
+ if (!dev_priv->pcigart_offset_set)
+ DRM_ERROR("Need gart offset from userspace\n");
+
+ dev_priv->gart_info.bus_addr =
+ dev_priv->pcigart_offset + dev_priv->fb_location;
+ dev_priv->gart_info.mapping.offset =
+ dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
+ dev_priv->gart_info.mapping.size =
+ dev_priv->gart_info.table_size;
- drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
+ drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
- dev_priv->gart_info.addr =
+ dev_priv->gart_info.addr =
dev_priv->gart_info.mapping.handle;
- DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
- dev_priv->gart_info.addr,
- dev_priv->pcigart_offset);
+ DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
+ dev_priv->gart_info.addr,
+ dev_priv->pcigart_offset);
+
+ r600_page_table_init(dev);
+ }
- r600_page_table_init(dev);
if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
r700_vm_init(dev);
r700_cp_load_microcode(dev_priv);
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 19ff1b6..7754804 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -144,15 +144,15 @@ void radeon_write_agp_location(drm_radeon_private_t
*dev_priv, u32 agp_loc)
RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
}
-static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
{
u32 agp_base_hi = upper_32_bits(agp_base);
u32 agp_base_lo = agp_base & 0xffffffff;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
- RADEON_WRITE(R700_MC_VM_AGP_BASE, 0); /* FIX ME */
+ RADEON_WRITE(R700_MC_VM_AGP_BASE, agp_base_lo); /* FIX ME */
else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
- RADEON_WRITE(R600_MC_VM_AGP_BASE, 0); /* FIX ME */
+ RADEON_WRITE(R600_MC_VM_AGP_BASE, agp_base_lo); /* FIX ME */
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index d22f6ed..fa4d9ed 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -438,6 +438,7 @@ extern long radeon_compat_ioctl(struct file *filp, unsigned
int cmd,
unsigned long arg);
void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
+void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc);
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(struct drm_device *dev);
Am Dienstag, den 30.12.2008, 10:41 -0500 schrieb Alex Deucher:
Looks like you have an AGP card. Those aren't supported at the moment
(PCIE only). I should probably add a check to the ddx to not try and
init the drm until we have r6xx AGP support.
I already figured this out myself, so i started hacking the drm code a
little bit: I adjusted all calculations with the pcigart scatter-gather
address within r600_cp.c to match the one in radeon_cp.c, this fixed the
kernel oops and even allows xserver with xvideo support to start.
Playing some MPEG with mplayer displays something which looks like
random pixel data, so i think the only thing missing is programming the
agpgart addresses into the hardware, but here my knowledge really stops.
A patch is attached, is AGP support something witch is showing up soon?
I can't wait to crash the xserver while watch videos with xv, and start
hacking the hardware directly.
Bye, Christian.
# Not currently on any branch.
# Changes to be committed:
# (use "git reset HEAD <file>..." to unstage)
#
# modified: shared-core/r600_cp.c
# modified: shared-core/radeon_cp.c
# modified: shared-core/radeon_drv.h
#
# Untracked files:
# (use "git add <file>..." to include in what will be committed)
#
# drm-agp.patch
# linux-core/Module.markers
# linux-core/modules.order
diff --git a/shared-core/r600_cp.c b/shared-core/r600_cp.c
index 6436ffc..a1320b9 100644
--- a/shared-core/r600_cp.c
+++ b/shared-core/r600_cp.c
@@ -470,10 +470,9 @@ static int r600_page_table_init(struct drm_device *dev)
memset(pci_gart, 0, max_pages * sizeof(u64));
for (i = 0; i < pages; i++) {
- entry->busaddr[i] = pci_map_single(dev->pdev,
- page_address(entry->
- pagelist[i]),
- PAGE_SIZE, PCI_DMA_TODEVICE);
+ entry->busaddr[i] = pci_map_single(dev->pdev,
+ page_address(entry->pagelist[i]),
+ PAGE_SIZE, PCI_DMA_TODEVICE);
if (entry->busaddr[i] == 0) {
DRM_ERROR("unable to map PCIGART pages!\n");
r600_page_table_cleanup(dev, gart_info);
@@ -2003,6 +2002,16 @@ static void r600_cp_init_ring_buffer(struct drm_device *
dev,
SET_RING_HEAD(dev_priv, 0);
dev_priv->ring.tail = 0;
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
+ (dev_priv->ring_rptr->offset
+ - dev->agp->base
+ + dev_priv->gart_vm_start)
+ >> 8);
+ RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 0);
+ } else
+#endif
{
struct drm_sg_mem *entry = dev->sg;
unsigned long tmp_ofs, page_ofs;
@@ -2029,9 +2038,23 @@ static void r600_cp_init_ring_buffer(struct drm_device *
dev,
dev_priv->ring.size_l2qw);
#endif
- ring_start = (dev_priv->cp_ring->offset
- - (unsigned long)dev->sg->virtual
- + dev_priv->gart_vm_start);
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ radeon_write_agp_base(dev_priv, dev->agp->base);
+
+ radeon_write_agp_location(dev_priv,
+ (((dev_priv->gart_vm_start - 1 +
+ dev_priv->gart_size) & 0xffff0000) |
+ (dev_priv->gart_vm_start >> 16)));
+
+ ring_start = (dev_priv->cp_ring->offset
+ - dev->agp->base
+ + dev_priv->gart_vm_start);
+ } else
+#endif
+ ring_start = (dev_priv->cp_ring->offset
+ - (unsigned long)dev->sg->virtual
+ + dev_priv->gart_vm_start);
RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
@@ -2279,6 +2302,18 @@ int r600_do_init_cp(struct drm_device * dev,
drm_radeon_init_t * init)
* location in the card and on the bus, though we have to
* align it down.
*/
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ base = dev->agp->base;
+ /* Check if valid */
+ if ((base + dev_priv->gart_size - 1) >=
dev_priv->fb_location &&
+ base < (dev_priv->fb_location + dev_priv->fb_size
- 1)) {
+ DRM_INFO("Can't use AGP base @0x%08lx, won't
fit\n",
+ dev->agp->base);
+ base = 0;
+ }
+ }
+#endif
/* If not or if AGP is at 0 (Macs), try to put it elsewhere */
if (base == 0) {
base = dev_priv->fb_location + dev_priv->fb_size;
@@ -2293,9 +2328,16 @@ int r600_do_init_cp(struct drm_device * dev,
drm_radeon_init_t * init)
base, dev_priv->gart_vm_start);
}
- dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
- - (unsigned long)dev->sg->virtual
- + dev_priv->gart_vm_start);
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP)
+ dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
+ - dev->agp->base
+ + dev_priv->gart_vm_start);
+ else
+#endif
+ dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
+ - (unsigned
long)dev->sg->virtual
+ + dev_priv->gart_vm_start);
DRM_DEBUG("fb 0x%08x size %d\n", dev_priv->fb_location,
dev_priv->fb_size);
DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
@@ -2319,28 +2361,38 @@ int r600_do_init_cp(struct drm_device * dev,
drm_radeon_init_t * init)
dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
- dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
- /* if we have an offset set from userspace */
- if (!dev_priv->pcigart_offset_set)
- DRM_ERROR("Need gart offset from userspace\n");
-
- dev_priv->gart_info.bus_addr =
- dev_priv->pcigart_offset + dev_priv->fb_location;
- dev_priv->gart_info.mapping.offset =
- dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
- dev_priv->gart_info.mapping.size =
- dev_priv->gart_info.table_size;
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ /* Turn off PCI GART */
+ //radeon_set_pcigart(dev_priv, 0);
+ } else
+#endif
+ {
+ dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
+
+ /* if we have an offset set from userspace */
+ if (!dev_priv->pcigart_offset_set)
+ DRM_ERROR("Need gart offset from userspace\n");
+
+ dev_priv->gart_info.bus_addr =
+ dev_priv->pcigart_offset + dev_priv->fb_location;
+ dev_priv->gart_info.mapping.offset =
+ dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
+ dev_priv->gart_info.mapping.size =
+ dev_priv->gart_info.table_size;
- drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
+ drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
- dev_priv->gart_info.addr =
+ dev_priv->gart_info.addr =
dev_priv->gart_info.mapping.handle;
- DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
- dev_priv->gart_info.addr,
- dev_priv->pcigart_offset);
+ DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
+ dev_priv->gart_info.addr,
+ dev_priv->pcigart_offset);
+
+ r600_page_table_init(dev);
+ }
- r600_page_table_init(dev);
if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
r700_vm_init(dev);
r700_cp_load_microcode(dev_priv);
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 19ff1b6..7754804 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -144,15 +144,15 @@ void radeon_write_agp_location(drm_radeon_private_t
*dev_priv, u32 agp_loc)
RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
}
-static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
{
u32 agp_base_hi = upper_32_bits(agp_base);
u32 agp_base_lo = agp_base & 0xffffffff;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
- RADEON_WRITE(R700_MC_VM_AGP_BASE, 0); /* FIX ME */
+ RADEON_WRITE(R700_MC_VM_AGP_BASE, agp_base_lo); /* FIX ME */
else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
- RADEON_WRITE(R600_MC_VM_AGP_BASE, 0); /* FIX ME */
+ RADEON_WRITE(R600_MC_VM_AGP_BASE, agp_base_lo); /* FIX ME */
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index d22f6ed..fa4d9ed 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -438,6 +438,7 @@ extern long radeon_compat_ioctl(struct file *filp, unsigned
int cmd,
unsigned long arg);
void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
+void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc);
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(struct drm_device *dev);
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