Mailinglist Archive: radeonhd (311 mails)
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RE: [radeonhd] any power saving modes possible?
- From: "Bridgman, John" <John.Bridgman@xxxxxxx>
- Date: Tue, 19 Feb 2008 12:38:20 -0500
- Message-id: <898503EB1E15BA4F944D1BE69D55AAC85E4182@xxxxxxxxxxxxxxxxx>
Yep, no argument there. We are just in the process of pushing PowerPlay
into the closed source drivers so we should have some experience to
leverage soon.
-----Original Message-----
From: Matthias Hopf [mailto:mhopf@xxxxxxx]
Sent: Tuesday, February 19, 2008 11:55 AM
To: radeonhd@xxxxxxxxxxxx
Cc: Bridgman, John; Deucher, Alexander
Subject: Re: [radeonhd] any power saving modes possible?
On Feb 19, 08 11:35:08 -0500, Bridgman, John wrote:
You're correct. We just haven't looked at that, probably because we
didn't have any use case for it so far.
OTOH we don't know how this call is actually used, and which limits
apply - there are entries in the FirmwareInfo, but they proved to be
somewhat unreliable for pixel clocks. And we all know how picky PLLs can
be when being programmed wrongly ;-) In contrast to pixel clock you also
don't see a wobbly clock immediately, it just might corrupt some
calculations.
Also there might be side effects, like you might have to reprogram
memory refresh etc.
All in all this is something that we have deliberately left as something
for future work. We could probably work something that works with the
current information available, but there are more pressing issues ATM.
CU
Matthias
--
Matthias Hopf <mhopf@xxxxxxx> __ __ __
Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__
mat@xxxxxxxxx
Phone +49-911-74053-715 __) |_| __) |__ R & D
www.mshopf.de
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into the closed source drivers so we should have some experience to
leverage soon.
-----Original Message-----
From: Matthias Hopf [mailto:mhopf@xxxxxxx]
Sent: Tuesday, February 19, 2008 11:55 AM
To: radeonhd@xxxxxxxxxxxx
Cc: Bridgman, John; Deucher, Alexander
Subject: Re: [radeonhd] any power saving modes possible?
On Feb 19, 08 11:35:08 -0500, Bridgman, John wrote:
Aren't there AtomBIOS calls for setting engine clock ?
You're correct. We just haven't looked at that, probably because we
didn't have any use case for it so far.
OTOH we don't know how this call is actually used, and which limits
apply - there are entries in the FirmwareInfo, but they proved to be
somewhat unreliable for pixel clocks. And we all know how picky PLLs can
be when being programmed wrongly ;-) In contrast to pixel clock you also
don't see a wobbly clock immediately, it just might corrupt some
calculations.
Also there might be side effects, like you might have to reprogram
memory refresh etc.
All in all this is something that we have deliberately left as something
for future work. We could probably work something that works with the
current information available, but there are more pressing issues ATM.
CU
Matthias
--
Matthias Hopf <mhopf@xxxxxxx> __ __ __
Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__
mat@xxxxxxxxx
Phone +49-911-74053-715 __) |_| __) |__ R & D
www.mshopf.de
--
To unsubscribe, e-mail: radeonhd+unsubscribe@xxxxxxxxxxxx For additional
commands, e-mail: radeonhd+help@xxxxxxxxxxxx
--
To unsubscribe, e-mail: radeonhd+unsubscribe@xxxxxxxxxxxx
For additional commands, e-mail: radeonhd+help@xxxxxxxxxxxx
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