Mailinglist Archive: radeonhd (622 mails)

[Xavier Bestel <xavier.bestel@xxxxxxx>]

On Mon, 2007-10-08 at 12:35 +0200, Syren Baran wrote:
> The R580 has (depending on modell) 48 processors each executing the same
> command on different memory locations (though some may be sleeping,
> depending on flow control).
> The instruction set is very different from architectures i know.
> A Sparcs RISC set is more or less a subset of x86 CISC set, but this ...
> hmm, i still consider it wierd, but maybe it just takes time getting
> used to.
> 
> LLVM docs state it can produce code for Sparc and x86 (and intermediate
> byte code) and mentions all kinds of optimisation strategies.
> I doubt these strategies were developed with such a processor in mind.

Ask Zack Rusin, he's working precisely on that:

http://www.nabble.com/Vector-swizzling-and-write-masks-code-generation-t4528538.html

        Xav


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