Mailinglist Archive: radeonhd (622 mails)
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[radeonhd] [ANNOUNCE] PLL Clock programming changes/ LVDS Panel info from AtomBIOS
- From: Egbert Eich <eich@xxxxxxx>
- Date: Sun, 7 Oct 2007 15:50:16 +0200
- Message-id: <18184.58392.141910.964465@xxxxxxxxxxxxxxxxxxx>
Hi!
This morning I've pushed two sets of changes into the radeonhd driver:
1. The driver now uses data about clock limit data in AtomBIOS for calculating
pixel clocks. This introduced additional limits to the clock values.
Also in a longer debugging session with Dongxu Li we decided to change
the algorithm for searching for valid PLL dividers and apporach the
RefClock divider from the top. This strategy will give us larger divider
values. It is expected that larger dividers will compensate better for clock
jitter and noise.
Still we are far from having solved all problems regarding clock
programming.
2. We get LVDS paramters for panels from AtomBIOS. Most (unfortunately not
all) data required to program the LVTMA for LVDS panels is contained
in AtomBIOS. The patch rerieves now retrieves the data from there
hopefully making device tables unnecessary (except for special cases).
The current code ignores the device tables completely (this is to
give the new code better testing exposure and will be changed later).
Please report bugs in the #xorg bugzilla, on radeonhd@xxxxxxxxxxxx or
in #radeonhd at freenode.net.
Cheers,
Egbert.
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