In fact, C compilers targets often build much better code for today's superscalar and/or RISC architectures than an assembler coder can. I certainly can attest to that. In general, the classic compiler is designed in 3 passes with the last being code generation. One many RISC architectures, including the Digital/Compaq/HP Alpha chip, there is another
On Sunday 11 June 2006 8:31 pm, Bryan J. Smith wrote:
pass called a scheduler. The scheduler looks at the instruction stream and
uses latency tables to reorder instructions to reduce latencies. The Alpha
could issue 4 instructions simultaneously, so the scheduler would try to
set up the groupings to optimize this. One reason why the high level
language (C, FORTRAN, etc) is better than assembler, is that eventhough
some assemblers do include the schedulers, the assembler coder can chose
register combinations that cause the scheduler not to be able to generate
the nest code.
On the down side, if you have ever tried to debug scheduled code, you will
find that it jumps all over the place.
Just a quick note regarding Intel's EPIC - many of the compiler people from
Digital/Compaq are currently at Intel. The EPIC architecture (eg IA64)
relies upon compiler technology.
--
Jerry Feldman