Hello community, here is the log from the commit of package xorg-x11-driver-video checked in at Fri Nov 3 19:05:29 CET 2006. -------- --- xorg-x11-driver-video/xorg-x11-driver-video.changes 2006-11-02 15:00:15.000000000 +0100 +++ /mounts/work_src_done/STABLE/xorg-x11-driver-video/xorg-x11-driver-video.changes 2006-11-03 16:49:56.000000000 +0100 @@ -1,0 +2,5 @@ +Fri Nov 3 16:49:45 CET 2006 - sndirsch@suse.de + +- updated intel modesetting driver (git_2006-11-03) + +------------------------------------------------------------------- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ xorg-x11-driver-video.spec ++++++ --- /var/tmp/diff_new_pack.oiIrnv/_old 2006-11-03 19:05:02.000000000 +0100 +++ /var/tmp/diff_new_pack.oiIrnv/_new 2006-11-03 19:05:02.000000000 +0100 @@ -14,7 +14,7 @@ BuildRequires: Mesa-devel libdrm-devel pkgconfig xorg-x11-proto-devel xorg-x11-server-sdk URL: http://xorg.freedesktop.org/ Version: 7.2 -Release: 11 +Release: 12 License: X11/MIT BuildRoot: %{_tmppath}/%{name}-%{version}-build Group: System/X11/Servers/XF86_4 @@ -204,6 +204,8 @@ %{_mandir}/man4/* %changelog -n xorg-x11-driver-video +* Fri Nov 03 2006 - sndirsch@suse.de +- updated intel modesetting driver (git_2006-11-03) * Thu Nov 02 2006 - sndirsch@suse.de - updated vmware driver to release 10.14.0 * Add Xinerama support. ++++++ xf86-video-intel.modesetting.tar.bz2 ++++++ diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/.gitignore new/xf86-video-intel.modesetting/.gitignore --- old/xf86-video-intel.modesetting/.gitignore 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/.gitignore 1970-01-01 01:00:00.000000000 +0100 @@ -1,23 +0,0 @@ -.deps -.libs -Makefile -Makefile.in -*.la -*.lo -*.o -aclocal.m4 -autom4te.cache -compile -config.guess -config.h -config.h.in -config.log -config.status -config.sub -configure -depcomp -install-sh -libtool -ltmain.sh -missing -stamp-h1 diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/.gitignore new/xf86-video-intel.modesetting/src/.gitignore --- old/xf86-video-intel.modesetting/src/.gitignore 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/.gitignore 1970-01-01 01:00:00.000000000 +0100 @@ -1,6 +0,0 @@ -.deps -.libs -Makefile -Makefile.in -*.la -*.lo diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/bios_reader/.gitignore new/xf86-video-intel.modesetting/src/bios_reader/.gitignore --- old/xf86-video-intel.modesetting/src/bios_reader/.gitignore 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/bios_reader/.gitignore 1970-01-01 01:00:00.000000000 +0100 @@ -1 +0,0 @@ -bios_reader diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/ch7xxx/ch7xxx.c new/xf86-video-intel.modesetting/src/ch7xxx/ch7xxx.c --- old/xf86-video-intel.modesetting/src/ch7xxx/ch7xxx.c 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/ch7xxx/ch7xxx.c 2006-11-03 16:39:18.000000000 +0100 @@ -38,7 +38,7 @@ #include "ch7xxx.h" #include "ch7xxx_reg.h" -static void ch7xxxSaveRegs(void *d); +static void ch7xxxSaveRegs(I2CDevPtr d); static CARD8 ch7xxxFreqRegs[][7] = { { 0, 0x23, 0x08, 0x16, 0x30, 0x60, 0x00 }, @@ -243,9 +243,9 @@ } } -static void ch7xxxSaveRegs(void *d) +static void ch7xxxSaveRegs(I2CDevPtr d) { - CH7xxxPtr ch7xxx = CH7PTR(((I2CDevPtr)d)); + CH7xxxPtr ch7xxx = CH7PTR(d); int ret; int i; diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/i810_reg.h new/xf86-video-intel.modesetting/src/i810_reg.h --- old/xf86-video-intel.modesetting/src/i810_reg.h 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/i810_reg.h 2006-11-03 16:39:18.000000000 +0100 @@ -276,11 +276,13 @@ #define GPIOG 0x5028 #define GPIOH 0x502c # define GPIO_CLOCK_DIR_MASK (1 << 0) +# define GPIO_CLOCK_DIR_IN (0 << 1) # define GPIO_CLOCK_DIR_OUT (1 << 1) # define GPIO_CLOCK_VAL_MASK (1 << 2) # define GPIO_CLOCK_VAL_OUT (1 << 3) # define GPIO_CLOCK_VAL_IN (1 << 4) # define GPIO_DATA_DIR_MASK (1 << 8) +# define GPIO_DATA_DIR_IN (0 << 9) # define GPIO_DATA_DIR_OUT (1 << 9) # define GPIO_DATA_VAL_MASK (1 << 10) # define GPIO_DATA_VAL_OUT (1 << 11) @@ -739,6 +741,7 @@ #define VSYNC_A 0x60014 #define PIPEASRC 0x6001c #define BCLRPAT_A 0x60020 +#define VSYNCSHIFT_A 0x60028 #define HTOTAL_B 0x61000 #define HBLANK_B 0x61004 @@ -748,6 +751,7 @@ #define VSYNC_B 0x61014 #define PIPEBSRC 0x6101c #define BCLRPAT_B 0x61020 +#define VSYNCSHIFT_B 0x61028 #define PP_STATUS 0x61200 # define PP_ON (1 << 31) @@ -849,6 +853,14 @@ # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 /** @} */ +#define DPLL_TEST 0x606c + +#define D_STATE 0x6104 +#define DSPCLK_GATE_D 0x6200 +#define RENCLK_GATE_D1 0x6204 +#define RENCLK_GATE_D2 0x6208 +#define RAMCLK_GATE_D 0x6210 /* CRL only */ + #define BLC_PWM_CTL 0x61254 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) @@ -856,6 +868,21 @@ #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) +#define BLM_CTL 0x61260 +#define BLM_THRESHOLD_0 0x61270 +#define BLM_THRESHOLD_1 0x61274 +#define BLM_THRESHOLD_2 0x61278 +#define BLM_THRESHOLD_3 0x6127c +#define BLM_THRESHOLD_4 0x61280 +#define BLM_THRESHOLD_5 0x61284 + +#define BLM_ACCUMULATOR_0 0x61290 +#define BLM_ACCUMULATOR_1 0x61294 +#define BLM_ACCUMULATOR_2 0x61298 +#define BLM_ACCUMULATOR_3 0x6129c +#define BLM_ACCUMULATOR_4 0x612a0 +#define BLM_ACCUMULATOR_5 0x612a4 + #define FPA0 0x06040 #define FPA1 0x06044 #define FPB0 0x06048 @@ -907,6 +934,13 @@ #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) #define SDVOC_PRESERVE_MASK (1 << 17) +#define UDIB_SVB_SHB_CODES 0x61144 +#define UDIB_SHA_BLANK_CODES 0x61148 +#define UDIB_START_END_FILL_CODES 0x6114c + + +#define SDVOUDI 0x61150 + #define I830_HTOTAL_MASK 0xfff0000 #define I830_HACTIVE_MASK 0x7ff @@ -1554,6 +1588,19 @@ #define PIPEACONF_GAMMA (1<<24) #define PIPECONF_FORCE_BORDER (1<<25) +#define PIPEAGCMAXRED 0x70010 +#define PIPEAGCMAXGREEN 0x70014 +#define PIPEAGCMAXBLUE 0x70018 +#define PIPEASTAT 0x70024 + +#define DSPARB 0x70030 +#define DSPFW1 0x70034 +#define DSPFW2 0x70038 +#define DSPFW3 0x7003c +#define PIPEAFRAMEHIGH 0x70040 +#define PIPEAFRAMEPIXEL 0x70044 + + #define PIPEBCONF 0x71008 #define PIPEBCONF_ENABLE (1<<31) #define PIPEBCONF_DISABLE 0 @@ -1562,6 +1609,13 @@ #define PIPEBCONF_GAMMA (1<<24) #define PIPEBCONF_PALETTE 0 +#define PIPEBGCMAXRED 0x71010 +#define PIPEBGCMAXGREEN 0x71014 +#define PIPEBGCMAXBLUE 0x71018 +#define PIPEBSTAT 0x71024 +#define PIPEBFRAMEHIGH 0x71040 +#define PIPEBFRAMEPIXEL 0x71044 + #define DSPACNTR 0x70180 #define DSPBCNTR 0x71180 #define DISPLAY_PLANE_ENABLE (1<<31) @@ -1598,6 +1652,9 @@ #define DSPBADDR DSPBBASE #define DSPBSTRIDE 0x71188 +#define DSPAKEYVAL 0x70194 +#define DSPAKEYMASK 0x70198 + #define DSPAPOS 0x7018C /* reserved */ #define DSPASIZE 0x70190 #define DSPBPOS 0x7118C diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/i830.h new/xf86-video-intel.modesetting/src/i830.h --- old/xf86-video-intel.modesetting/src/i830.h 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/i830.h 2006-11-03 16:39:18.000000000 +0100 @@ -397,7 +397,6 @@ int MonType1; int MonType2; - Bool specifiedMonitor; DGAModePtr DGAModes; int numDGAModes; diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/i830_debug.c new/xf86-video-intel.modesetting/src/i830_debug.c --- old/xf86-video-intel.modesetting/src/i830_debug.c 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/i830_debug.c 2006-11-03 16:39:18.000000000 +0100 @@ -41,6 +41,25 @@ char *name; CARD32 regval; } i830_snapshot[] = { + DEFINEREG(VCLK_DIVISOR_VGA0), + DEFINEREG(VCLK_DIVISOR_VGA1), + DEFINEREG(VCLK_POST_DIV), + DEFINEREG(DPLL_TEST), + DEFINEREG(D_STATE), + DEFINEREG(DSPCLK_GATE_D), + DEFINEREG(RENCLK_GATE_D1), + DEFINEREG(RENCLK_GATE_D2), +/* DEFINEREG(RAMCLK_GATE_D), CRL only */ + DEFINEREG(SDVOB), + DEFINEREG(SDVOC), +/* DEFINEREG(UDIB_SVB_SHB_CODES), CRL only */ +/* DEFINEREG(UDIB_SHA_BLANK_CODES), CRL only */ + DEFINEREG(SDVOUDI), + DEFINEREG(DSPARB), + DEFINEREG(DSPFW1), + DEFINEREG(DSPFW2), + DEFINEREG(DSPFW3), + DEFINEREG(ADPA), DEFINEREG(LVDS), DEFINEREG(DVOA), @@ -62,36 +81,46 @@ DEFINEREG(DSPAPOS), DEFINEREG(DSPASIZE), DEFINEREG(DSPABASE), + DEFINEREG(DSPASURF), + DEFINEREG(DSPATILEOFF), DEFINEREG(PIPEACONF), DEFINEREG(PIPEASRC), DEFINEREG(FPA0), DEFINEREG(FPA1), DEFINEREG(DPLL_A), + DEFINEREG(DPLL_A_MD), DEFINEREG(HTOTAL_A), DEFINEREG(HBLANK_A), DEFINEREG(HSYNC_A), DEFINEREG(VTOTAL_A), DEFINEREG(VBLANK_A), DEFINEREG(VSYNC_A), + DEFINEREG(BCLRPAT_A), + DEFINEREG(VSYNCSHIFT_A), DEFINEREG(DSPBCNTR), DEFINEREG(DSPBSTRIDE), DEFINEREG(DSPBPOS), DEFINEREG(DSPBSIZE), DEFINEREG(DSPBBASE), + DEFINEREG(DSPBSURF), + DEFINEREG(DSPBTILEOFF), DEFINEREG(PIPEBCONF), DEFINEREG(PIPEBSRC), DEFINEREG(FPB0), DEFINEREG(FPB1), DEFINEREG(DPLL_B), + DEFINEREG(DPLL_B_MD), DEFINEREG(HTOTAL_B), DEFINEREG(HBLANK_B), DEFINEREG(HSYNC_B), DEFINEREG(VTOTAL_B), DEFINEREG(VBLANK_B), DEFINEREG(VSYNC_B), + DEFINEREG(BCLRPAT_B), + DEFINEREG(VSYNCSHIFT_B), DEFINEREG(VCLK_DIVISOR_VGA0), DEFINEREG(VCLK_DIVISOR_VGA1), @@ -129,13 +158,115 @@ } } +static void i830DumpIndexed (ScrnInfoPtr pScrn, char *name, int id, int val, int min, int max) +{ + I830Ptr pI830 = I830PTR(pScrn); + int i; + + for (i = min; i <= max; i++) { + OUTREG8 (id, i); + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "%18.18s%02x: 0x%02x\n", + name, i, INREG8(val)); + } +} + void i830DumpRegs (ScrnInfoPtr pScrn) { I830Ptr pI830 = I830PTR(pScrn); int i; + int fp, dpll; + int pipe; + int n, m1, m2, m, p1, p2; + int ref; + int dot; + int phase; + int msr; + int crt; + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "DumpRegsBegin\n"); for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) { - xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "%10.10s: 0x%08x\n", + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "%20.20s: 0x%08x\n", i830_snapshot[i].name, (unsigned int) INREG(i830_snapshot[i].reg)); } + i830DumpIndexed (pScrn, "SR", 0x3c4, 0x3c5, 0, 7); + msr = INREG8(0x3cc); + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "%20.20s: 0x%02x\n", + "MSR", (unsigned int) msr); + + if (msr & 1) + crt = 0x3d0; + else + crt = 0x3b0; + i830DumpIndexed (pScrn, "CR", crt + 4, crt + 5, 0, 0x24); + for (pipe = 0; pipe <= 1; pipe++) + { + fp = INREG(pipe == 0 ? FPA0 : FPB0); + dpll = INREG(pipe == 0 ? DPLL_A : DPLL_B); + switch ((dpll >> 24) & 0x3) { + case 0: + p2 = 10; + break; + case 1: + p2 = 5; + break; + default: + p2 = 1; + xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "p2 out of range\n"); + break; + } + switch ((dpll >> 16) & 0xff) { + case 1: + p1 = 1; break; + case 2: + p1 = 2; break; + case 4: + p1 = 3; break; + case 8: + p1 = 4; break; + case 16: + p1 = 5; break; + case 32: + p1 = 6; break; + case 64: + p1 = 7; break; + case 128: + p1 = 8; break; + default: + p1 = 1; + xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "p1 out of range\n"); + break; + } + switch ((dpll >> 13) & 0x3) { + case 0: + ref = 96000; + break; + default: + ref = 0; + xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "ref out of range\n"); + break; + } + phase = (dpll >> 9) & 0xf; + switch (phase) { + case 6: + break; + default: + xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "phase %d out of range\n", phase); + break; + } + switch ((dpll >> 8) & 1) { + case 0: + break; + default: + xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "fp select out of range\n"); + break; + } + n = ((fp >> 16) & 0x3f); + m1 = ((fp >> 8) & 0x3f); + m2 = ((fp >> 0) & 0x3f); + m = 5 * (m1 + 2) + (m2 + 2); + dot = (ref * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)) / (p1 * p2); + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "pipe %s dot %d n %d m1 %d m2 %d p1 %d p2 %d\n", + pipe == 0 ? "A" : "B", dot, n, m1, m2, p1, p2); + } + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "DumpRegsEnd\n"); } diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/i830_display.c new/xf86-video-intel.modesetting/src/i830_display.c --- old/xf86-video-intel.modesetting/src/i830_display.c 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/i830_display.c 2006-11-03 16:39:18.000000000 +0100 @@ -607,6 +607,16 @@ pI830->output[i].post_set_mode(pScrn, &pI830->output[i], pMode); } + /* + * If the panel fitter is stuck on our pipe, turn it off + * the LVDS output will whack it correctly if it needs it + */ + if (((INREG(PFIT_CONTROL) >> 29) & 0x3) == pipe) + OUTREG(PFIT_CONTROL, 0); + + OUTREG(PFIT_PGM_RATIOS, 0x10001000); + OUTREG(DSPARB, (47 << 0) | (95 << 7)); + OUTREG(htot_reg, htot); OUTREG(hblank_reg, hblank); OUTREG(hsync_reg, hsync); diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/i830_driver.c new/xf86-video-intel.modesetting/src/i830_driver.c --- old/xf86-video-intel.modesetting/src/i830_driver.c 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/i830_driver.c 2006-11-03 16:39:18.000000000 +0100 @@ -1279,7 +1279,6 @@ pI830->MonType1 = PIPE_NONE; pI830->MonType2 = PIPE_NONE; - pI830->specifiedMonitor = FALSE; if ((s = xf86GetOptValString(pI830->Options, OPTION_MONITOR_LAYOUT)) && I830IsPrimary(pScrn)) { @@ -1366,7 +1365,6 @@ pI830->pipe = 1; pI830->operatingDevices = (pI830->MonType2 << 8) | pI830->MonType1; - pI830->specifiedMonitor = TRUE; } else if (I830IsPrimary(pScrn)) { /* Choose a default set of outputs to use based on what we've detected. * @@ -2310,6 +2308,8 @@ pI830->saveSWF[15] = INREG(SWF31); pI830->saveSWF[16] = INREG(SWF32); + pI830->savePFIT_CONTROL = INREG(PFIT_CONTROL); + for (i = 0; i < pI830->num_outputs; i++) { if (pI830->output[i].save != NULL) pI830->output[i].save(pScrn, &pI830->output[i]); @@ -2428,6 +2428,8 @@ OUTREG(SWF31, pI830->saveSWF[15]); OUTREG(SWF32, pI830->saveSWF[16]); + OUTREG(PFIT_CONTROL, pI830->savePFIT_CONTROL); + i830CompareRegsToSnapshot(pScrn); return TRUE; diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/i830_i2c.c new/xf86-video-intel.modesetting/src/i830_i2c.c --- old/xf86-video-intel.modesetting/src/i830_i2c.c 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/i830_i2c.c 2006-11-03 16:39:18.000000000 +0100 @@ -48,6 +48,219 @@ #include "shadow.h" #include "i830.h" +#define AIRLIED_I2C 0 + +#if AIRLIED_I2C + +#define I2C_TIMEOUT(x) /*(x)*/ /* Report timeouts */ +#define I2C_TRACE(x) /*(x)*/ /* Report progress */ + +static void i830_setscl(I2CBusPtr b, int state) +{ + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + I830Ptr pI830 = I830PTR(pScrn); + CARD32 val; + + OUTREG(b->DriverPrivate.uval, + (state ? GPIO_CLOCK_VAL_OUT : 0) | GPIO_CLOCK_DIR_OUT | + GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK); + val = INREG(b->DriverPrivate.uval); +} + +static void i830_setsda(I2CBusPtr b, int state) +{ + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + I830Ptr pI830 = I830PTR(pScrn); + CARD32 val; + + OUTREG(b->DriverPrivate.uval, + (state ? GPIO_DATA_VAL_OUT : 0) | GPIO_DATA_DIR_OUT | + GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK); + val = INREG(b->DriverPrivate.uval); +} + +static void i830_getscl(I2CBusPtr b, int *state) +{ + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + I830Ptr pI830 = I830PTR(pScrn); + CARD32 val; + + OUTREG(b->DriverPrivate.uval, GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK); + OUTREG(b->DriverPrivate.uval, 0); + val = INREG(b->DriverPrivate.uval); + *state = ((val & GPIO_DATA_VAL_IN) != 0); +} + +static int i830_getsda(I2CBusPtr b) + { + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + I830Ptr pI830 = I830PTR(pScrn); + CARD32 val; + + OUTREG(b->DriverPrivate.uval, GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK); + OUTREG(b->DriverPrivate.uval, 0); + val = INREG(b->DriverPrivate.uval); + return ((val & GPIO_DATA_VAL_IN) != 0); +} + +static inline void sdalo(I2CBusPtr b) +{ + i830_setsda(b, 0); + b->I2CUDelay(b, b->RiseFallTime); +} + +static inline void sdahi(I2CBusPtr b) +{ + i830_setsda(b, 1); + b->I2CUDelay(b, b->RiseFallTime); +} + +static inline void scllo(I2CBusPtr b) +{ + i830_setscl(b, 0); + b->I2CUDelay(b, b->RiseFallTime); +} + +static inline int sclhi(I2CBusPtr b, int timeout) +{ + int scl = 0; + int i; + + i830_setscl(b, 1); + b->I2CUDelay(b, b->RiseFallTime); + + for (i = timeout; i > 0; i -= b->RiseFallTime) { + i830_getscl(b, &scl); + if (scl) break; + b->I2CUDelay(b, b->RiseFallTime); + } + + if (i <= 0) { + I2C_TIMEOUT(ErrorF("[I2CRaiseSCL(<%s>, %d) timeout]", + b->BusName, timeout)); + return FALSE; + } + return TRUE; +} + +static Bool +I830I2CGetByte(I2CDevPtr d, I2CByte *data, Bool last) +{ + I2CBusPtr b = d->pI2CBus; + int i, sda; + unsigned char indata = 0; + + sdahi(b); + + for (i = 0; i < 8; i++) { + if (sclhi(b, d->BitTimeout) == FALSE) { + I2C_TRACE(ErrorF("timeout at bit #%d\n", 7-i)); + return FALSE; + }; + indata *= 2; + if (i830_getsda(b)) + indata |= 0x01; + scllo(b); + } + + if (last) { + sdahi(b); + } else { + sdalo(b); + } + + if (sclhi(b, d->BitTimeout) == FALSE) { + sdahi(b); + return FALSE; + }; + + scllo(b); + sdahi(b); + + *data = indata & 0xff; + I2C_TRACE(ErrorF("R%02x ", (int) *data)); + + return TRUE; +} + +static Bool +I830I2CPutByte(I2CDevPtr d, I2CByte c) +{ + Bool r; + int i, scl, sda; + int sb, ack; + I2CBusPtr b = d->pI2CBus; + + for (i = 7; i >= 0; i--) { + sb = c & (1 << i); + i830_setsda(b, sb); + b->I2CUDelay(b, b->RiseFallTime); + + if (sclhi(b, d->ByteTimeout) == FALSE) { + sdahi(b); + return FALSE; + } + + i830_setscl(b, 0); + b->I2CUDelay(b, b->RiseFallTime); + } + sdahi(b); + if (sclhi(b, d->ByteTimeout) == FALSE) { + I2C_TIMEOUT(ErrorF("[I2CPutByte(<%s>, 0x%02x, %d, %d, %d) timeout]", + b->BusName, c, d->BitTimeout, + d->ByteTimeout, d->AcknTimeout)); + return FALSE; + } + ack = i830_getsda(b); + I2C_TRACE(ErrorF("Put byte 0x%02x , getsda() = %d\n", c & 0xff, ack)); + + scllo(b); + return (0 == ack); +} + +static Bool +I830I2CStart(I2CBusPtr b, int timeout) +{ + if (sclhi(b, timeout) == FALSE) + return FALSE; + + sdalo(b); + scllo(b); + + return TRUE; +} + +static void +I830I2CStop(I2CDevPtr d) +{ + I2CBusPtr b = d->pI2CBus; + + sdalo(b); + sclhi(b, d->ByteTimeout); + sdahi(b); +} + +static Bool +I830I2CAddress(I2CDevPtr d, I2CSlaveAddr addr) +{ + if (I830I2CStart(d->pI2CBus, d->StartTimeout)) { + if (I830I2CPutByte(d, addr & 0xFF)) { + if ((addr & 0xF8) != 0xF0 && + (addr & 0xFE) != 0x00) + return TRUE; + + if (I830I2CPutByte(d, (addr >> 8) & 0xFF)) + return TRUE; + } + + I830I2CStop(d); + } + + return FALSE; +} + +#else + static void i830I2CGetBits(I2CBusPtr b, int *clock, int *data) { @@ -76,6 +289,7 @@ GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK); } +#endif /* the i830 has a number of I2C Buses */ Bool @@ -90,8 +304,16 @@ pI2CBus->BusName = name; pI2CBus->scrnIndex = pScrn->scrnIndex; +#if AIRLIED_I2C + pI2CBus->I2CGetByte = I830I2CGetByte; + pI2CBus->I2CPutByte = I830I2CPutByte; + pI2CBus->I2CStart = I830I2CStart; + pI2CBus->I2CStop = I830I2CStop; + pI2CBus->I2CAddress = I830I2CAddress; +#else pI2CBus->I2CGetBits = i830I2CGetBits; pI2CBus->I2CPutBits = i830I2CPutBits; +#endif pI2CBus->DriverPrivate.uval = i2c_reg; if (!xf86I2CBusInit(pI2CBus)) diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/i830_lvds.c new/xf86-video-intel.modesetting/src/i830_lvds.c --- old/xf86-video-intel.modesetting/src/i830_lvds.c 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/i830_lvds.c 2006-11-03 16:39:18.000000000 +0100 @@ -86,7 +86,6 @@ { I830Ptr pI830 = I830PTR(pScrn); - pI830->savePFIT_CONTROL = INREG(PFIT_CONTROL); pI830->savePP_ON = INREG(LVDSPP_ON); pI830->savePP_OFF = INREG(LVDSPP_OFF); pI830->saveLVDS = INREG(LVDS); @@ -115,7 +114,6 @@ OUTREG(LVDSPP_ON, pI830->savePP_ON); OUTREG(LVDSPP_OFF, pI830->savePP_OFF); OUTREG(PP_CYCLE, pI830->savePP_CYCLE); - OUTREG(PFIT_CONTROL, pI830->savePFIT_CONTROL); OUTREG(LVDS, pI830->saveLVDS); OUTREG(PP_CONTROL, pI830->savePP_CONTROL); if (pI830->savePP_CONTROL & POWER_TARGET_ON) diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/i830_sdvo.c new/xf86-video-intel.modesetting/src/i830_sdvo.c --- old/xf86-video-intel.modesetting/src/i830_sdvo.c 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/i830_sdvo.c 2006-11-03 16:39:18.000000000 +0100 @@ -553,7 +553,7 @@ output_dtd.part2.sync_off_width_high = 0; output_dtd.part2.dtd_flags = 0x18; output_dtd.part2.sdvo_flags = 0; - output_dtd.part2.v_sync_off_width = 0; + output_dtd.part2.v_sync_off_high = 0; output_dtd.part2.reserved = 0; if (mode->Flags & V_PHSYNC) output_dtd.part2.dtd_flags |= 0x2; diff -urN --exclude=CVS --exclude=.cvsignore --exclude=.svn --exclude=.svnignore old/xf86-video-intel.modesetting/src/xvmc/.gitignore new/xf86-video-intel.modesetting/src/xvmc/.gitignore --- old/xf86-video-intel.modesetting/src/xvmc/.gitignore 2006-11-02 14:54:52.000000000 +0100 +++ new/xf86-video-intel.modesetting/src/xvmc/.gitignore 1970-01-01 01:00:00.000000000 +0100 @@ -1,6 +0,0 @@ -.deps -.libs -Makefile -Makefile.in -*.la -*.lo ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Remember to have fun... --------------------------------------------------------------------- To unsubscribe, e-mail: opensuse-commit+unsubscribe@opensuse.org For additional commands, e-mail: opensuse-commit+help@opensuse.org