On Tue, 20 Jan 2004 12:13:15 -0000 daniel.kidger@quadrics.com wrote:
Hi, We have noticed a default mtrr on our Quartet nodes (kernel=2.4.21-171 with both 4GB and 8GB RAM)
# cat /proc/mtrr reg01: base=0xc0000000 (3072MB), size=1024MB: uncachable, count=1
Why is this uncachable mtrr setting made?
The kernel doesn't do it, it comes from the BIOS. Ask your motherboard vendor.
- it isn't there on dual CPU nodes (Celestica and Newisys - both 2GB RAM):
$ cat /proc/mtrr reg00: base=0x00000000 ( 0MB), size=2048MB: write-back, count=1
We have a PCI device that can get tremendous performance improvements if we enable write-combining to its on board memory and registers. But we cannot change the mtrr settings against its BARs due to this uncachable mapping. e.g. when we do
echo 'base=0xe0000000 size=0x10000000 type=write-combining' >| /proc/mtrr
we get this dmesg;
mtrr: type mismatch for e0000000,10000000 old: uncachable new: write-combining
Disabling this uncachable mapping and then replacing it with new ones generally causes the node to hang or crash.
Doe anyone know if there is a way to enable write-combining for our device BARs ?
Remove the uncacheable mtrr, add a wc one for your BAR and add new uncacheable ones for the rest that was previously covered by the uncacheable mtrr. -Andi